laczipmixer\mc9s12d64equ.inc

freescale的资料

BK0V5:      equ   %00100000
BK0V4:      equ   %00010000
BK0V3:      equ   %00001000
BK0V2:      equ   %00000100
BK0V1:      equ   %00000010
BK0V0:      equ   %00000001

BKP0H:      equ   $2B         ;BKP first address high byte reg

BKP0L:      equ   $2C         ;BKP first address low byte reg

BKP1X:      equ   $2D         ;BKP second address expansion reg

BK1V5:      equ   %00100000
BK1V4:      equ   %00010000
BK1V3:      equ   %00001000
BK1V2:      equ   %00000100
BK1V1:      equ   %00000010
BK1V0:      equ   %00000001

BKP1H:      equ   $2E         ;BKP data 2nd addr high byte reg

BKP1L:      equ   $2F         ;BKP data 2nd addr low byte reg



;****  MMC map 4 of 4 (Module Mapping Control, Device User Guide) ***************************
;*
PPAGE:      equ   $30         ;program page index register
;
PIX5:       equ   %00100000   ;program page index bits 5
PIX4:       equ   %00010000   ;program page index bits 4
PIX3:       equ   %00001000   ;program page index bits 3
PIX2:       equ   %00000100   ;program page index bits 2
PIX1:       equ   %00000010   ;program page index bits 1
PIX0:       equ   %00000001   ;program page index bits 0

; $31 reserved



;****  MEBI map 3 of 3 (Multiplex External Bus Interface) ***********************************
;*
PORTK:      equ   $32         ;I/O port K 8-bit data register
;
PTK7:       equ   %10000000   ;port K bit 7
PTK6:       equ   %01000000   ;port K bit 6
PTK5:       equ   %00100000   ;port K bit 5
PTK4:       equ   %00010000   ;port K bit 4
PTK3:       equ   %00001000   ;port K bit 3
PTK2:       equ   %00000100   ;port K bit 2
PTK1:       equ   %00000010   ;port K bit 1
PTK0:       equ   %00000001   ;port K bit 0

DDRK:       equ   $33         ;I/O portK 8-bit data direction reg
; 
DDRK7:      equ   %10000000   ;port K bit 7
DDRK6:      equ   %01000000   ;port K bit 6
DDRK5:      equ   %00100000   ;port K bit 5
DDRK4:      equ   %00010000   ;port K bit 4
DDRK3:      equ   %00001000   ;port K bit 3
DDRK2:      equ   %00000100   ;port K bit 2
DDRK1:      equ   %00000010   ;port K bit 1
DDRK0:      equ   %00000001   ;port K bit 0



;****  Clock and Reset Generator (PLL, RTI, COP)  *******************************************
;*
SYNR:       equ   $34         ;CRG synthesizer register
;
SYN5:       equ   %00100000     
SYN4:       equ   %00010000     
SYN3:       equ   %00001000     
SYN2:       equ   %00000100     
SYN1:       equ   %00000010     
SYN0:       equ   %00000001     

REFDV:      equ   $35         ;CRG reference divider register
;
REFDV3:     equ   %00001000     
REFDV2:     equ   %00000100     
REFDV1:     equ   %00000010     
REFDV0:     equ   %00000001     

CTFLG:      equ   $36         ;reserved reg (test only)
;
TOUT7:      equ   %10000000     
TOUT6:      equ   %01000000     
TOUT5:      equ   %00100000     
TOUT4:      equ   %00010000     
TOUT3:      equ   %00001000     
TOUT2:      equ   %00000100     
TOUT1:      equ   %00000010     
TOUT0:      equ   %00000001     

CRGFLG:     equ   $37         ;CRG flags register
;
RTIF:       equ   %10000000   ;real time interrupt flag
PORF:       equ   %01000000   ;power on reset flag
LVRF:       equ   %00100000   ;low voltage reset flag
LOCKIF:     equ   %00010000   ;PLL lock interrupt flag
LOCK:       equ   %00001000   ;lock status bit
TRACK:      equ   %00000100   ;track status bit
SCMIF:      equ   %00000010   ;self clock mode interrupt flag
SCM:        equ   %00000001   ;self clock mode status bit

CRGINT:     equ   $38         ;CRG interrupt enable register
;
RTIE:       equ   %10000000   ;real time interrupt enable bit
LOCKIE:     equ   %00010000   ;lock interrupt enable bit
SCMIE:      equ   %00000010   ;self clock mode INT enable bit

CLKSEL:     equ   $39         ;CRG clock select register
;
PLLSEL:     equ   %10000000   ;PLL select bit
PSTP:       equ   %01000000   ;pseudo stop bit
SYSWAI:     equ   %00100000   ;sys clocks stop in wait mode bit
ROAWAI:     equ   %00010000   ;reduced OSC amp in wait mode bit
PLLWAI:     equ   %00001000   ;PLL stops in wait mode bit
CWAI:       equ   %00000100   ;core stops in wait mode bit
RTIWAI:     equ   %00000010   ;RTI stops in wait mode bit
COPWAI:     equ   %00000001   ;COP stops in wait mode bit

PLLCTL:     equ   $3A         ;CRG PLL control register
;
CME:        equ   %10000000   ;clock monitor enable bit
PLLON:      equ   %01000000   ;phase lock loop on bit
AUTO:       equ   %00100000   ;automatic bandwidth control bit
ACQ:        equ   %00010000   ;acquisition bit
PRE:        equ   %00000100   ;RTI enable during pseudo stop
PCE:        equ   %00000010   ;COP enable during pseudo stop
SCME:       equ   %00000001   ;RTI enable during pseudo stop bit

RTICTL:     equ   $3B         ;CRG RTI control register
;
RTR6:       equ   %01000000   ;real time INT prescale rate select
RTR5:       equ   %00100000   ;real time INT prescale rate select
RTR4:       equ   %00010000   ;real time INT prescale rate select
RTR3:       equ   %00001000   ;real time INT modulus CNT select
RTR2:       equ   %00000100   ;real time INT modulus CNT select
RTR1:       equ   %00000010   ;real time INT modulus CNT select
RTR0:       equ   %00000001   ;real time INT modulus CNT select

COPCTL:     equ   $3C         ;CRG COP control register
;
WCOP:       equ   %10000000   ;window COP mode bit
RSBCK:      equ   %01000000   ;COP RTI stop in active BDM mode
CR2:        equ   %00000100   ;COP watchdog timer rate select
CR1:        equ   %00000010   ;COP watchdog timer rate select
CR0:        equ   %00000001   ;COP watchdog timer rate select

FORBYP:     equ   $3D         ;reserved register (test only)

CTCTL:      equ   $3E         ;reserved register (test only)

ARMCOP:     equ   $3F         ;CRG COP timer arm/reset register
;
ARMCOP7:    equ   %10000000     
ARMCOP6:    equ   %01000000     
ARMCOP5:    equ   %00100000     
ARMCOP4:    equ   %00010000     
ARMCOP3:    equ   %00001000     
ARMCOP2:    equ   %00000100     
ARMCOP1:    equ   %00000010     
ARMCOP0:    equ   %00000001



;****  Enhanced Capture Timer 16-bit 8 channels (TIM0)  *************************************
;*
T0TIOS:     equ   $40         ;timer input cap/output comp select
;
IOS7:       equ   %10000000   ;input cap/output comp chan config
IOS6:       equ   %01000000   ;input cap/output comp chan config
IOS5:       equ   %00100000   ;input cap/output comp chan config
IOS4:       equ   %00010000   ;input cap/output comp chan config
IOS3:       equ   %00001000   ;input cap/output comp chan config
IOS2:       equ   %00000100   ;input cap/output comp chan config
IOS1:       equ   %00000010   ;input cap/output comp chan config
IOS0:       equ   %00000001   ;input cap/output comp chan config

T0CFORC:    equ   $41         ;timer compare force register
;
FOC7:       equ   %10000000   ;force output comp action for ch 7
FOC6:       equ   %01000000   ;force output comp action for ch 6
FOC5:       equ   %00100000   ;force output comp action for ch 5
FOC4:       equ   %00010000   ;force output comp action for ch 4
FOC3:       equ   %00001000   ;force output comp action for ch 3
FOC2:       equ   %00000100   ;force output comp action for ch 2
FOC1:       equ   %00000010   ;force output comp action for ch 1
FOC0:       equ   %00000001   ;force output comp action for ch 0

T0OC7M:     equ   $42         ;output compare 7 mask register
;
OC7M7:      equ   %10000000   ;output compare 7 mask 7 channel
OC7M6:      equ   %01000000   ;output compare 7 mask 6 channel
OC7M5:      equ   %00100000   ;output compare 7 mask 5 channel
OC7M4:      equ   %00010000   ;output compare 7 mask 4 channel
OC7M3:      equ   %00001000   ;output compare 7 mask 3 channel
OC7M2:      equ   %00000100   ;output compare 7 mask 2 channel
OC7M1:      equ   %00000010   ;output compare 7 mask 1 channel
OC7M0:      equ   %00000001   ;output compare 7 mask 0 channel

T0OC7D:     equ   $43         ;output compare 7 data register
;
OC7D7:      equ   %10000000   ;output compare 7 data for ch 7
OC7D6:      equ   %01000000   ;output compare 7 data for ch 6
OC7D5:      equ   %00100000   ;output compare 7 data for ch 5
OC7D4:      equ   %00010000   ;output compare 7 data for ch 4
OC7D3:      equ   %00001000   ;output compare 7 data for ch 3
OC7D2:      equ   %00000100   ;output compare 7 data for ch 2
OC7D1:      equ   %00000010   ;output compare 7 data for ch 1
OC7D0:      equ   %00000001   ;output compare 7 data for ch 0

T0TCNT:     equ   $44         ;timer count register

; FREE RUNNING COUNTER TCNT IS A 16-BIT REGISTER ($44:$45)

T0TSCR1:    equ   $46         ;timer system control register 1
;
TEN:        equ   %10000000   ;timer enable
TSWAI:      equ   %01000000   ;timer module stops while in wait
TSFRZ:      equ   %00100000   ;timer stops while in freeze mode
TFFCA:      equ   %00010000   ;timer fast flag clear all

T0TTOV:     equ   $47         ;timer toggle on overflow reg 1
;
TOV7:       equ   %10000000   ;toggle on overflow bit
TOV6:       equ   %01000000   ;toggle on overflow bit
TOV5:       equ   %00100000   ;toggle on overflow bit
TOV4:       equ   %00010000   ;toggle on overflow bit
TOV3:       equ   %00001000   ;toggle on overflow bit
TOV2:       equ   %00000100   ;toggle on overflow bit
TOV1:       equ   %00000010   ;toggle on overflow bit
TOV0:       equ   %00000001   ;toggle on overflow bit

T0TCTL1:    equ   $48         ;timer control register 1
;
OM7:        equ   %10000000   ;output mode bit7
OL7:        equ   %01000000   ;output level bit7
OM6:        equ   %00100000   ;output mode bit6
OL6:        equ   %00010000   ;output level bit6
OM5:        equ   %00001000   ;output mode bit5
OL5:        equ   %00000100   ;output level bit5
OM4:        equ   %00000010   ;output mode bit4
OL4:        equ   %00000001   ;output level bit4

T0TCTL2:    equ   $49         ;timer control register 2
;
OM3:        equ   %10000000   ;output mode bit3
OL3:        equ   %01000000   ;output level bit3
OM2:        equ   %00100000   ;output mode bit2
OL2:        equ   %00010000   ;output level bit2
OM1:        equ   %00001000   ;output mode bit1
OL1:        equ   %00000100   ;output level bit1
OM0:        equ   %00000010   ;output mode bit0
OL0:        equ   %00000001   ;output level bit0

T0TCTL3:    equ   $4A         ;timer control register 3
;
EDG7B:      equ   %10000000   ;input capture edge control
EDG7A:      equ   %01000000   ;input capture edge control
EDG6B:      equ   %00100000   ;input capture edge control
EDG6A:      equ   %00010000   ;input capture edge control
EDG5B:      equ   %00001000   ;input capture edge control
EDG5A:      equ   %00000100   ;input capture edge control
EDG4B:      equ   %00000010   ;input capture edge control
EDG4A:      equ   %00000001   ;input capture edge control

T0TCTL4:    equ   $4B         ;timer control register 4 
;
EDG3B:      equ   %10000000   ;input capture edge control
EDG3A:      equ   %01000000   ;input capture edge control
EDG2B:      equ   %00100000   ;input capture edge control
EDG2A:      equ   %00010000   ;input capture edge control
EDG1B:      equ   %00001000   ;input capture edge control
EDG1A:      equ   %00000100   ;input capture edge control
EDG0B:      equ   %00000010   ;input capture edge control
EDG0A:      equ   %00000001   ;input capture edge control


T0TIE:      equ   $4C         ;timer interrupt enable register
;
C7I:        equ   %10000000   ;input cap/output comp INT enable
C6I:        equ   %01000000   ;input cap/output comp INT enable
C5I:        equ   %00100000   ;input cap/output comp INT enable
C4I:        equ   %00010000   ;input cap/output comp INT enable
C3I:        equ   %00001000   ;input cap/output comp INT enable
C2I:        equ   %00000100   ;input cap/output comp INT enable
C1I:        equ   %00000010   ;input cap/output comp INT enable
C0I:        equ   %00000001   ;input cap/output comp INT enable

T0TSCR2:    equ   $4D         ;timer system control register 2
;
TOI:        equ   %10000000   ;timer overflow interrupt enable
TCRE:       equ   %00001000   ;timer counter reset enable
PR2:        equ   %00000100   ;timer prescaler select
PR1:        equ   %00000010   ;timer prescaler select
PR0:        equ   %00000001   ;timer prescaler select

T0TFLG1:    equ   $4E         ;main timer interrupt flag 1
;
C7F:        equ   %10000000   ;input cap/output comp channel flag
C6F:        equ   %01000000   ;input cap/output comp channel flag
C5F:        equ   %00100000   ;input cap/output comp channel flag
C4F:        equ   %00010000   ;input cap/output comp channel flag
C3F:        equ   %00001000   ;input cap/output comp channel flag
C2F:        equ   %00000100   ;input cap/output comp channel flag
C1F:        equ   %00000010   ;input cap/output comp channel flag
C0F:        equ   %00000001   ;input cap/output comp channel flag

T0TFLG2:    equ   $4F         ;main timer interrupt flag 2
;
TOF:        equ   %10000000   ;timer overflow flag

T0TC0:      equ   $50         ;timer input cap/output comp reg

; TIMER CHANNEL 0 REGISTER TC0 IS A 16-BIT REGISTER ($50:$51)

T0TC1:      equ   $52         ;timer input cap/output comp reg

; TIMER CHANNEL 1 REGISTER TC1 IS A 16-BIT REGISTER ($52:$53)

T0TC2:      equ   $54         ;timer input cap/output comp reg

; TIMER CHANNEL 2 REGISTER TC2 IS A 16-BIT REGISTER ($54:$55)

T0TC3:      equ   $56         ;timer input cap/output comp reg

; TIMER CHANNEL 3 REGISTER TC3 IS A 16-BIT REGISTER ($56:$57)

T0TC4:      equ   $58         ;timer input cap/output comp reg

; TIMER CHANNEL 4 REGISTER TC4 IS A 16-BIT REGISTER ($58:$59)

T0TC5:      equ   $5A         ;timer input cap/output comp reg

; TIMER CHANNEL 5 REGISTER TC5 IS A 16-BIT REGISTER ($5A:$5B)

T0TC6:      equ   $5C         ;timer input cap/output comp reg

; TIMER CHANNEL 6 REHISTER TC6 IS A 16-BIT REGISTER ($5C:$5D)

T0TC7:      equ   $5E         ;timer input cap/output comp reg