laczipmixer\mc9s12d64equ.inc

freescale的资料

;********************************************************************************************
;* Title: MCS12D64.inc                            (c) MOTOROLA Inc. 2003 All rights reserved
;********************************************************************************************
;* Author:  LOU DILLARD - Motorola TSPG
;*
;* Description:  Register and bit name definitions for MC9S12D64
;*
;* Documentation: 9S12DJ64 Device User Guide V01.12 
;*
;* Include files:  none
;*
;* Assembler:  Metrowerks Code Warrior 3.0 
;*             or P&E Microcomputer Systems - CASM12Z
;*
;* Revision History:
;* Rev #      Date       Who     Comments
;* ------  -----------   ------  ------------------------------------------------------------
;* 1.2      03-Sep-03    L-Dill  reformatted columns AN2111
;* 1.1      14-Aug-03    L-Dill  change file extension
;* 1.0      19-Jun-03    L-Dill  initial file release
;********************************************************************************************



;****  Interrupt Vectors  *******************************************************************
;*
Vpwm8b8csd: equ   $FF8C       ;PWM shutdown
Vportp:     equ   $FF8E       ;port P  
Vmscan0xmit:
            equ   $FFB0       ;MSCAN 0 transmit  
Vmscan0rcv: equ   $FFB2       ;MSCAN 0 receive  
Vmscan0err: equ   $FFB4       ;MSCAN 0 error  
Vmscan0wkup:
            equ   $FFB6       ;MSCAN 0 wake-up
Vflash:     equ   $FFB8       ;FLASH
Veeprom:    equ   $FFBA       ;EEPROM
Viic:       equ   $FFC0       ;IIC bus 
Vcrgscm:    equ   $FFC4       ;CRG self clock mode 
Vcrgplllck: equ   $FFC6       ;CRG PLL lock 
Vectpbovfl: equ   $FFC8       ;pulse accumulator B overflow
Vectmdc:    equ   $FFCA       ;modulus down counter underflow  
Vporth:     equ   $FFCC       ;port H  
Vportj:     equ   $FFCE       ;port J
Vatd1:      equ   $FFD0       ;ATD1  
Vatd0:      equ   $FFD2       ;ATD0
Vsci1:      equ   $FFD4       ;SCI1
Vsci0:      equ   $FFD6       ;SCI0
Vspi0:      equ   $FFD8       ;SPI0
Vectpaedge: equ   $FFDA       ;pulse accumulator input edge
Vectpaovfl: equ   $FFDC       ;pulse accumulator A overflow  
Vectovrflw: equ   $FFDE       ;timer overflow  
Vectch7:    equ   $FFE0       ;timer 0 channel 7  
Vectch6:    equ   $FFE2       ;timer 0 channel 6  
Vectch5:    equ   $FFE4       ;timer 0 channel 5  
Vectch4:    equ   $FFE6       ;timer 0 channel 4  
Vectch3:    equ   $FFE8       ;timer 0 channel 3
Vectch2:    equ   $FFEA       ;timer 0 channel 2   
Vectch1:    equ   $FFEC       ;timer 0 channel 1   
Vectch0:    equ   $FFEE       ;timer 0 channel 0
Vrti:       equ   $FFF0       ;real time interrupt  
Virq:       equ   $FFF2       ;IRQ
Vxirq:      equ   $FFF4       ;XIRQ
Vswi:       equ   $FFF6       ;SWI
Vtrap:      equ   $FFF8       ;unimplemented instruction trap  
Vcop:       equ   $FFFA       ;COP failure reset  
Vclkmntr:   equ   $FFFC       ;clock monitor fail reset
Vreset:     equ   $FFFE       ;reset vector



;****  MEBI map 1 of 3 (Multiplex External Bus Interface) ***********************************
;*
PORTA:      equ   $00         ;I/O port A 8-bit data register
; 
PTA7:       equ   %10000000   ;port A bit 7
PTA6:       equ   %01000000   ;port A bit 6
PTA5:       equ   %00100000   ;port A bit 5
PTA4:       equ   %00010000   ;port A bit 4
PTA3:       equ   %00001000   ;port A bit 3
PTA2:       equ   %00000100   ;port A bit 2
PTA1:       equ   %00000010   ;port A bit 1
PTA0:       equ   %00000001   ;port A bit 0

PORTB:      equ   $01         ;I/O port B 8-bit data register
; 
PTB7:       equ   %10000000   ;port B bit 7
PTB6:       equ   %01000000   ;port B bit 6
PTB5:       equ   %00100000   ;port B bit 5
PTB4:       equ   %00010000   ;port B bit 4
PTB3:       equ   %00001000   ;port B bit 3
PTB2:       equ   %00000100   ;port B bit 2
PTB1:       equ   %00000010   ;port B bit 1
PTB0:       equ   %00000001   ;port B bit 0

DDRA:       equ   $02         ;I/O portA 8-bit data direction reg
; 
DDRA7:      equ   %10000000   ;port A bit 7
DDRA6:      equ   %01000000   ;port A bit 6
DDRA5:      equ   %00100000   ;port A bit 5
DDRA4:      equ   %00010000   ;port A bit 4
DDRA3:      equ   %00001000   ;port A bit 3
DDRA2:      equ   %00000100   ;port A bit 2
DDRA1:      equ   %00000010   ;port A bit 1
DDRA0:      equ   %00000001   ;port A bit 0

DDRB:       equ   $03         ;I/O portB 8-bit data direction reg
; 
DDRB7:      equ   %10000000   ;port B bit 7
DDRB6:      equ   %01000000   ;port B bit 6
DDRB5:      equ   %00100000   ;port B bit 5
DDRB4:      equ   %00010000   ;port B bit 4
DDRB3:      equ   %00001000   ;port B bit 3
DDRB2:      equ   %00000100   ;port B bit 2
DDRB1:      equ   %00000010   ;port B bit 1
DDRB0:      equ   %00000001   ;port B bit 0

; $04 to $07 reserved

PORTE:      equ   $08         ;I/O port E 8-bit data register
;
PTE7:       equ   %10000000   ;port E bit 7
PTE6:       equ   %01000000   ;port E bit 6
PTE5:       equ   %00100000   ;port E bit 5
PTE4:       equ   %00010000   ;port E bit 4
PTE3:       equ   %00001000   ;port E bit 3
PTE2:       equ   %00000100   ;port E bit 2
PTE1:       equ   %00000010   ;port E bit 1
PTE0:       equ   %00000001   ;port E bit 0

DDRE:       equ   $09         ;I/O port E 8-bit data direction reg
; 
DDRE7:      equ   %10000000   ;port E bit 7
DDRE6:      equ   %01000000   ;port E bit 6
DDRE5:      equ   %00100000   ;port E bit 5
DDRE4:      equ   %00010000   ;port E bit 4
DDRE3:      equ   %00001000   ;port E bit 3
DDRE2:      equ   %00000100   ;port E bit 2
DDRE1:      equ   %00000010   ;port E bit 1
DDRE0:      equ   %00000001   ;port E bit 0

PEAR:       equ   $0A         ;port E assignment register
;
NOACCE:     equ   %10000000   ;CPU no access output enable
PIPOE:      equ   %00100000   ;pipe status signal output enable
NECLK:      equ   %00010000   ;no external E clock
LSTRE:      equ   %00001000   ;low strobe (LSTRB) enable
RDWE:       equ   %00000100   ;read/write enable

MODE:       equ   $0B         ;establish mode of operation
;
MODC:       equ   %10000000   ;mode select bit C
MODB:       equ   %01000000   ;mode select bit B
MODA:       equ   %00100000   ;mode select bit A
IVIS:       equ   %00001000   ;internal visibility 
EMK:        equ   %00000010   ;emulate port K
EME:        equ   %00000001   ;emulate port E

PUCR:       equ   $0C         ;pullup control register
;
PUPKE:      equ   %10000000   ;pullup port K enable
PUPEE:      equ   %00010000   ;pullup port E enable
PUPBE:      equ   %00000010   ;pullup port B enable
PUPAE:      equ   %00000001   ;pullup port A enable

RDRIV:      equ   $0D         ;reduce drive register
;
RDPK:       equ   %10000000   ;reduced drive of port K
RDPE:       equ   %00010000   ;reduced drive of port E
RDPB:       equ   %00000010   ;reduced drive of port B
RDPA:       equ   %00000001   ;reduced drive of port A

EBICTL:     equ   $0E         ;external bus interface control reg
;
ESTR:       equ   %00000001   ;E clock stretches

; $0F reserved



;****  MMC map 1 of 4 (Module Mapping Control) **********************************************
;*
INITRM:     equ   $10         ;init of internal RAM position reg
;
RAM15:      equ   %10000000   ;internal register map position
RAM14:      equ   %01000000   ;internal register map position
RAM13:      equ   %00100000   ;internal register map position
RAM12:      equ   %00010000   ;internal register map position
RAM11:      equ   %00001000   ;internal register map position
RAMHAL:     equ   %00000001   ;RAM high-align

INITRG:     equ   $11         ;init of internal register position
;
REG14:      equ   %01000000   ;internal register map position
REG13:      equ   %00100000   ;internal register map position
REG12:      equ   %00010000   ;internal register map position
REG11:      equ   %00001000   ;internal register map position

INITEE:     equ   $12         ;init of internal EEPROM reg pos
;
EE15:       equ   %10000000   ;internal EEPROM map position
EE14:       equ   %01000000   ;internal EEPROM map position
EE13:       equ   %00100000   ;internal EEPROM map position
EE12:       equ   %00010000   ;internal EEPROM map position
EE11:       equ   %00001000   ;internal EEPROM map position
EEON:       equ   %00000001   ;enable EEPROM

MISC:       equ   $13         ;misc reg to config sys functions
;
EXSTR1:     equ   %10000000   ;external access stretch bit 1
EXSTR0:     equ   %01000000   ;external access stretch bit 0
ROMHM:      equ   %00100000   ;flash EEPROM or ROM
ROMON:      equ   %00010000   ;enable flash EEPROM or ROM

; $14 reserved



;****  INT map 1 of 2 (Interrupt control) ***************************************************
;*
ITCR:       equ   $15         ;interrupt test control register
;
WRINT:      equ   %00010000   ;write to the INT test registers
ADR3:       equ   %00001000   ;test register select bit
ADR2:       equ   %00000100   ;test register select bit
ADR1:       equ   %00000010   ;test register select bit
ADR0:       equ   %00000001   ;test register select bit

ITEST:      equ   $16         ;interrupt test register
;
INTE:       equ   %10000000   ;interrupt TEST bit E
INTC:       equ   %01000000   ;interrupt TEST bit C
INTA:       equ   %00100000   ;interrupt TEST bit A
INT8:       equ   %00010000   ;interrupt TEST bit 8
INT6:       equ   %00001000   ;interrupt TEST bit 6
INT4:       equ   %00000100   ;interrupt TEST bit 4
INT2:       equ   %00000010   ;interrupt TEST bit 2
INT0:       equ   %00000001   ;interrupt TEST bit 0



;****  MMC map 2 of 4 (Core User Guide)  ****************************************************
;*
; $17 reserved



;****  Miscellaneous Peripherals (Device User Guide) ****************************************
;*
; $18 reserved                  ;reserve for peripheral block reg

; $19 reserved 

PARTIDH:    equ   $1A         ;device ID high register
;
ID15:       equ   %10000000
ID14:       equ   %01000000
ID13:       equ   %00100000
ID12:       equ   %00010000
ID11:       equ   %00001000
ID10:       equ   %00000100
ID9:        equ   %00000010
ID8:        equ   %00000001

PARTIDL:    equ   $1B         ;device ID low register
;
ID7:        equ   %10000000
ID6:        equ   %01000000
ID5:        equ   %00100000
ID4:        equ   %00010000
ID3:        equ   %00001000
ID2:        equ   %00000100
ID1:        equ   %00000010
ID0:        equ   %00000001



;****  MMC map 3 of 4 (Module Mapping Control, Device User Guide) ***************************
;*
MEMSIZ0:    equ   $1C         ;memory size register 0
;
reg_sw0:    equ   %10000000   ;allocated system register space
eep_sw1:    equ   %00100000   ;allocated sys EEPROM memory space
eep_sw0:    equ   %00010000   ;allocated sys EEPROM memory space
ram_sw2:    equ   %00000100   ;allocated system RAM memory space
ram_sw1:    equ   %00000010   ;allocated system RAM memory space
ram_sw0:    equ   %00000001   ;allocated system RAM memory space

MEMSIZ1:    equ   $1D         ;MEMSIZ reg 1 (flash EEPROM or ROM)
;
rom_sw1:    equ   %10000000   ;allocated sys physical MEM space
rom_sw0:    equ   %01000000   ;allocated sys physical MEM space
pag_sw1:    equ   %00000010   ;allocated off-chip MEM space
pag_sw0:    equ   %00000001   ;allocated off-chip flash MEM space



;****  MEBI map 2 of 3 (Multiplex External Bus Interface) ***********************************
;*
IRQCR:      equ   $1E         ;IRQ control register
;
IRQE:       equ   %10000000   ;IRQ select edge sensitive only 
IRQEN:      equ   %01000000   ;external IRQ enable



;****  INT map 2 of 2 (Interrupt control) ***************************************************
;*
HPRIO:      equ   $1F         ;highest priority I interrupt reg
;
PSEL7:      equ   %10000000     
PSEL6:      equ   %01000000     
PSEL5:      equ   %00100000     
PSEL4:      equ   %00010000     
PSEL3:      equ   %00001000     
PSEL2:      equ   %00000100     
PSEL1:      equ   %00000010      



; $20 to $27 reserved



;****  BKP (Core User Guide)  ***************************************************************
;*
BKPCT0:     equ   $28         ;breakpoint control register 0
;
BKEN:       equ   %10000000   ;breakpoint enable
BKFULL:     equ   %01000000   ;full breakpoint mode enable
BKBDM:      equ   %00100000   ;BKP background debug mode enable
BKTAG:      equ   %00010000   ;breakpoint on tag

BKPCT1:     equ   $29         ;breakpoint control register 1
;
BK0MBH:     equ   %10000000   ;BKP mask high byte for 1st addr
BK0MBL:     equ   %01000000   ;BKP mask low byte for first addr
BK1MBH:     equ   %00100000   ;BKP mask high byte of data 2nd add
BK1MBL:     equ   %00010000   ;BKP mask low byte of data 2nd addr
BK0RWE:     equ   %00001000   ;R/W compare enable 0
BK0RW:      equ   %00000100   ;R/W compare value 0
BK1RWE:     equ   %00000010   ;R/W compare enable 1
BK1RW:      equ   %00000001   ;R/W compare value 1

BKP0X:      equ   $2A         ;BKP first address expansion reg
;