bcd8.prjfpg

altium designer09设计教程+原理图+PCB实例

[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=Out
LogFolderPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
TimestampOutput=0
SeparateFolders=0
PinSwapBy_Netlabel=1
PinSwapBy_Pin=1
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AppendSheetNumberToLocalNets=0
DefaultConfiguration=
UserID=0xFFFFFFFF
DefaultPcbProtel=1
DefaultPcbPcad=0
ReorderDocumentsOnCompile=1
NameNetsHierarchically=1
PowerPortNamesTakePriority=0
PushECOToAnnotationFile=1
VHDL87=0
Verilog95=0

[Document1]
DocumentPath=TestBCD.VHDTST
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document2]
DocumentPath=BCD.VHD
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document3]
DocumentPath=BCD8.schdoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document4]
DocumentPath=Parity.vhd
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document5]
DocumentPath=Utility.vhd
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document6]
DocumentPath=Bufgs.vhd
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document7]
DocumentPath=SCH Library\Bcd.schlib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[GeneratedDocument1]
DocumentPath=BCD8.SO

[GeneratedDocument2]
DocumentPath=BCD8.VHD

[SearchPath1]
Path=VHDL Models\*.*
IncludeSubFolders=1

[Generic_VHDLSynthesis]
Tool=nVisage Synthesizer
SettingsModified=False
Entity=BCD8
Architecture=
PromptedNewSynthesizer=False
SchematicNetlister=0
Insert IO Buffers=True
Default Enumeration Encoding=Default
Resource Sharing=True
FSM Compiler=True
Maximum Fanout=100
Optimization Goal=Area
Optimization Level=1
Frequency=0
Don't push Tristates across Process/Block boundaries=True
Keep Hierarchy=True
Infer Macrocells=False
Macrocell Kind=Coregen
Map Logic=True
Pack IO Registers into IOBs=Auto
Ram Style=Auto
Register Duplication=True
Write Mapped VHDL Netlist=False
Write Mapped Verilog Netlist=False
Write Vendor Constraint File=True
Include Synopsys Library=True
Include IEEE Numeric STD Library=False
Report Inferred Operators=False
Report Optimization Messages=False

[Generic_Quartus_sh]
Configuration Device=AUTO
Configuration Scheme=PASSIVE_SERIAL
Optimization Technique=BALANCED
Register Packing=NORMAL
Fitter Effort=AUTO FIT
Ignore Clock Settings=False
Optimize Timing=NORMAL COMPILATION

[Generic_VHDLSimulationWatches]
WatchName0=CLEAR
WatchEnable0=True
WatchWave0=True
WatchName1=CLOCK
WatchEnable1=True
WatchWave1=True
WatchName2=ENABLE
WatchEnable2=True
WatchWave2=True
WatchName3=LOWER
WatchEnable3=True
WatchWave3=True
WatchName4=Parity
WatchEnable4=True
WatchWave4=True
WatchName5=UPPER
WatchEnable5=True
WatchWave5=True
WatchName6=URCO
WatchEnable6=True
WatchWave6=True

[Generic_VHDLSimulation]
Tool=DXP Simulator
NoIEEE=False
VHDL93=True
Verilog2001=True
TopLevelEntity=TestBCD
TopLevelArchitecture=Stimulus
TopLevelUnit=TestBCD.VHDTST
RunToTime=20000000000
SDFInstance=
SDFFileName=
SDFOptimization=0
SettingsModified=False
TimeStep=1000000000000
TimeUnits=ms
RunToUnits=ns

[OutputGroup1]
Name=Netlist Outputs
Description=
TargetPrinter=Microsoft XPS Document Writer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=ProtelNetlist
OutputName1=Protel
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=EDIF
OutputName2=EDIF for PCB
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=MultiWire
OutputName3=MultiWire
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
OutputType4=Pcad
OutputName4=Pcad for PCB
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
OutputType5=VHDL
OutputName5=VHDL File
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
Configuration5_Name1=OutputConfigurationParameter1
Configuration5_Item1=Crossprobe=False|EnableAttributes=True|Record=VHDLView|SingleFile=True
OutputType6=XSpiceNetlist
OutputName6=XSpice Netlist
OutputDocumentPath6=
OutputVariantName6=
OutputDefault6=0
OutputType7=Verilog
OutputName7=Verilog File
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
OutputType8=CadnetixNetlist
OutputName8=Cadnetix Netlist
OutputDocumentPath8=
OutputVariantName8=
OutputDefault8=0
OutputType9=CalayNetlist
OutputName9=Calay Netlist
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=EESofNetlist
OutputName10=EESof Netlist
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=IntergraphNetlist
OutputName11=Intergraph Netlist
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=MentorBoardStationNetlist
OutputName12=Mentor BoardStation Netlist
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=OrCadPCB2Netlist
OutputName13=Orcad/PCB2 Netlist
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=PADSNetlist
OutputName14=PADS ASCII Netlist
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=PCADNetlist
OutputName15=PCAD Netlist
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=PCADnltNetlist
OutputName16=PCADnlt Netlist
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=Protel2Netlist
OutputName17=Protel2 Netlist
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=RacalNetlist
OutputName18=Racal Netlist
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
OutputType19=RINFNetlist
OutputName19=RINF Netlist
OutputDocumentPath19=
OutputVariantName19=
OutputDefault19=0
OutputType20=SciCardsNetlist
OutputName20=SciCards Netlist
OutputDocumentPath20=
OutputVariantName20=
OutputDefault20=0
OutputType21=SIMetrixNetlist
OutputName21=SIMetrix
OutputDocumentPath21=
OutputVariantName21=
OutputDefault21=0
OutputType22=SIMPLISNetlist
OutputName22=SIMPLIS