bufgs.vhd

来自「altium designer09设计教程+原理图+PCB实例」· VHDL 代码 · 共 16 行

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library IEEE;
use IEEE.std_logic_1164.all;

entity BUFGS is
  port(I : in std_logic;
       O : out std_logic);
end BUFGS;

architecture RTL of BUFGS is
begin
  O <= I;
end;
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