fpga_project1.edf

altium designer09设计教程+原理图+PCB实例

            (Property Simulation (String "SN74LS32" ))
            (Property Footprint (String "D014_N" ))
            (Property Description (String "Quadruple 2-Input Positive-OR Gate" ))
            (Property UniqueId (String "\XPUNOKPL" ))
            (Property PhysicalPath (String "Sheet1" ))
            (Property ChannelOffset (String "2" ))
          )
          (Instance U4
            (viewRef NetlistView
              (cellRef SN74LS04D
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Code_IPC (String "SOIC127P600-14" ))
            (Property Comment (String "SN74LS04D" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property ComponentLink1Description (String "Manufacturer Link" ))
            (Property ComponentLink1URL (String "http://www.ti.com/" ))
            (Property ComponentLink2Description (String "Datasheet" ))
            (Property ComponentLink2URL (String "http://www-s.ti.com/sc/ds/sn74ls04.pdf" ))
            (Property DatasheetVersion (String "Mar-1988" ))
            (Property Description (String "Hex Inverter" ))
            (Property Footprint (String "D014_N" ))
            (Property LatestRevisionDate (String "13-Apr-2006" ))
            (Property LatestRevisionNote (String "IPC-7351 Footprint Added." ))
            (Property (rename Library_Name "Library Name") (String "TI Logic Gate 2.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "SN74LS04D" ))
            (Property PackageDescription (String "14-Pin Small Outline Integrated Circuit 1.27 mm Pitch" ))
            (Property PackageReference (String "D014" ))
            (Property PackageVersion (String "Jan-1998" ))
            (Property PCB3D (String "D014" ))
            (Property Published (String "8-Jun-2000" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "SN74LS04D" ))
            (Property Simulation (String "SN74LS04" ))
            (Property Footprint (String "D014_N" ))
            (Property Description (String "Hex Inverter" ))
            (Property UniqueId (String "\CBJGBFJF" ))
            (Property PhysicalPath (String "Sheet1" ))
            (Property ChannelOffset (String "3" ))
          )
          (Instance U5
            (viewRef NetlistView
              (cellRef SN74LS173AD
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Code_IPC (String "SOIC127P600-16" ))
            (Property Comment (String "SN74LS173AD" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property ComponentLink1Description (String "Manufacturer Link" ))
            (Property ComponentLink1URL (String "http://www.ti.com/" ))
            (Property ComponentLink2Description (String "Datasheet" ))
            (Property ComponentLink2URL (String "http://www-s.ti.com/sc/ds/sn74ls173a.pdf" ))
            (Property DatasheetVersion (String "Mar-1988" ))
            (Property Description (String "4-Bit D-Type Register with 3-State Outputs" ))
            (Property Footprint (String "D016_N" ))
            (Property LatestRevisionDate (String "13-Apr-2006" ))
            (Property LatestRevisionNote (String "IPC-7351 Footprint Added." ))
            (Property (rename Library_Name "Library Name") (String "TI Logic Flip-Flop.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "SN74LS173AD" ))
            (Property PackageDescription (String "16-Pin Small Outline Integrated Circuit 1.27 mm Pitch" ))
            (Property PackageReference (String "D016" ))
            (Property PackageVersion (String "Jan-1998" ))
            (Property PCB3D (String "D016" ))
            (Property Published (String "8-Jun-2000" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "SN74LS173AD" ))
            (Property Simulation (String "SN74LS173" ))
            (Property Footprint (String "D016_N" ))
            (Property Description (String "4-Bit D-Type Register with 3-State Outputs" ))
            (Property UniqueId (String "\EHDDLWBT" ))
            (Property PhysicalPath (String "Sheet1" ))
            (Property ChannelOffset (String "4" ))
          )
          (Net VCC
            (Joined 
                (PortRef &14 (InstanceRef U1))
                (PortRef &14 (InstanceRef U2))
                (PortRef &14 (InstanceRef U3))
                (PortRef &14 (InstanceRef U4))
            )
          )
          (Net NetU1_2
            (Joined 
                (PortRef &2 (InstanceRef U1))
                (PortRef &10 (InstanceRef U1))
                (PortRef &2 (InstanceRef U2))
                (PortRef &2 (InstanceRef U4))
            )
          )
          (Net NetU1_3
            (Joined 
                (PortRef &3 (InstanceRef U1))
                (PortRef &4 (InstanceRef U3))
            )
          )
          (Net NetU1_5
            (Joined 
                (PortRef &5 (InstanceRef U1))
            )
          )
          (Net NetU1_6
            (Joined 
                (PortRef &6 (InstanceRef U1))
                (PortRef &5 (InstanceRef U3))
            )
          )
          (Net NetU1_8
            (Joined 
                (PortRef &8 (InstanceRef U1))
                (PortRef &1 (InstanceRef U3))
            )
          )
          (Net NetU1_9
            (Joined 
                (PortRef &9 (InstanceRef U1))
                (PortRef &12 (InstanceRef U1))
                (PortRef &1 (InstanceRef U4))
                (PortRef &5 (InstanceRef U4))
            )
          )
          (Net NetU1_11
            (Joined 
                (PortRef &11 (InstanceRef U1))
                (PortRef &2 (InstanceRef U3))
            )
          )
          (Net NetU2_3
            (Joined 
                (PortRef &3 (InstanceRef U2))
                (PortRef &4 (InstanceRef U2))
            )
          )
          (Net NetU2_5
            (Joined 
                (PortRef &5 (InstanceRef U2))
            )
          )
          (Net NetU2_6
            (Joined 
                (PortRef &6 (InstanceRef U2))
                (PortRef &10 (InstanceRef U3))
            )
          )
          (Net NetU3_3
            (Joined 
                (PortRef &3 (InstanceRef U3))
                (PortRef &9 (InstanceRef U3))
            )
          )
          (Net NetU4_3
            (Joined 
                (PortRef &3 (InstanceRef U4))
            )
          )
          (Net NetU4_6
            (Joined 
                (PortRef &6 (InstanceRef U4))
            )
          )
          (Net NetU5_2
            (Joined 
                (PortRef &2 (InstanceRef U5))
                (PortRef &9 (InstanceRef U5))
                (PortRef &10 (InstanceRef U5))
                (PortRef &11 (InstanceRef U5))
                (PortRef &15 (InstanceRef U5))
            )
          )
          (Net H3
            (Joined 
                (PortRef &1 (InstanceRef U1))
                (PortRef &1 (InstanceRef U2))
                (PortRef &4 (InstanceRef U4))
                (PortRef &14 (InstanceRef U5))
            )
          )
          (Net H2
            (Joined 
                (PortRef &8 (InstanceRef U3))
                (PortRef &12 (InstanceRef U5))
            )
          )
          (Net H1
            (Joined 
                (PortRef &6 (InstanceRef U3))
                (PortRef &1 (InstanceRef U5))
            )
          )
          (Net GND
            (Joined 
                (PortRef &7 (InstanceRef U1))
                (PortRef &7 (InstanceRef U2))
                (PortRef &7 (InstanceRef U3))
                (PortRef &7 (InstanceRef U4))
            )
          )
          (Net CLK
            (Joined 
                (PortRef &4 (InstanceRef U1))
                (PortRef &13 (InstanceRef U1))
                (PortRef &3 (InstanceRef U5))
                (PortRef &4 (InstanceRef U5))
                (PortRef &5 (InstanceRef U5))
                (PortRef &6 (InstanceRef U5))
                (PortRef &7 (InstanceRef U5))
                (PortRef &8 (InstanceRef U5))
                (PortRef &16 (InstanceRef U5))
            )
          )
       )
     )
   )
  )
  (design FPGA_Project1_PrjFpg
    (cellRef Sheet1_Sch
      (libraryRef SHEET_LIB)
    )
  )
)