📄 fpga_project1.edf
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(edif FPGA_Project1_PrjFpg
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2010 5 27 16 50 35)
(program "Altium Designer - EDIF For PCB"
(version "1.0.0")
)
(author "EDIF For PCB")
)
)
(library COMPONENT_LIB
(edifLevel 0)
(technology
(numberDefinition
(scale 1 1 (unit distance))
)
)
(cell SN74LS04D
(cellType GENERIC)
(view netListView
(viewType NETLIST)
(interface
(port (rename &1 "1") (direction INPUT))
(port (rename &2 "2") (direction OUTPUT))
(port (rename &3 "3") (direction INPUT))
(port (rename &4 "4") (direction OUTPUT))
(port (rename &5 "5") (direction INPUT))
(port (rename &6 "6") (direction OUTPUT))
(port (rename &7 "7") (direction INOUT))
(port (rename &8 "8") (direction OUTPUT))
(port (rename &9 "9") (direction INPUT))
(port (rename &10 "10") (direction OUTPUT))
(port (rename &11 "11") (direction INPUT))
(port (rename &12 "12") (direction OUTPUT))
(port (rename &13 "13") (direction INPUT))
(port (rename &14 "14") (direction INOUT))
)
)
)
(cell SN74LS08D
(cellType GENERIC)
(view netListView
(viewType NETLIST)
(interface
(port (rename &1 "1") (direction INPUT))
(port (rename &2 "2") (direction INPUT))
(port (rename &3 "3") (direction OUTPUT))
(port (rename &4 "4") (direction INPUT))
(port (rename &5 "5") (direction INPUT))
(port (rename &6 "6") (direction OUTPUT))
(port (rename &7 "7") (direction INOUT))
(port (rename &8 "8") (direction OUTPUT))
(port (rename &9 "9") (direction INPUT))
(port (rename &10 "10") (direction INPUT))
(port (rename &11 "11") (direction OUTPUT))
(port (rename &12 "12") (direction INPUT))
(port (rename &13 "13") (direction INPUT))
(port (rename &14 "14") (direction INOUT))
)
)
)
(cell SN74LS32D
(cellType GENERIC)
(view netListView
(viewType NETLIST)
(interface
(port (rename &1 "1") (direction INPUT))
(port (rename &2 "2") (direction INPUT))
(port (rename &3 "3") (direction OUTPUT))
(port (rename &4 "4") (direction INPUT))
(port (rename &5 "5") (direction INPUT))
(port (rename &6 "6") (direction OUTPUT))
(port (rename &7 "7") (direction INOUT))
(port (rename &8 "8") (direction OUTPUT))
(port (rename &9 "9") (direction INPUT))
(port (rename &10 "10") (direction INPUT))
(port (rename &11 "11") (direction OUTPUT))
(port (rename &12 "12") (direction INPUT))
(port (rename &13 "13") (direction INPUT))
(port (rename &14 "14") (direction INOUT))
)
)
)
(cell SN74LS173AD
(cellType GENERIC)
(view netListView
(viewType NETLIST)
(interface
(port (rename &1 "1") (direction INPUT))
(port (rename &2 "2") (direction INPUT))
(port (rename &3 "3") (direction INOUT))
(port (rename &4 "4") (direction INOUT))
(port (rename &5 "5") (direction INOUT))
(port (rename &6 "6") (direction INOUT))
(port (rename &7 "7") (direction INPUT))
(port (rename &8 "8") (direction INOUT))
(port (rename &9 "9") (direction INPUT))
(port (rename &10 "10") (direction INPUT))
(port (rename &11 "11") (direction INPUT))
(port (rename &12 "12") (direction INPUT))
(port (rename &13 "13") (direction INPUT))
(port (rename &14 "14") (direction INPUT))
(port (rename &15 "15") (direction INPUT))
(port (rename &16 "16") (direction INOUT))
)
)
)
)
(library SHEET_LIB
(edifLevel 0)
(technology
(numberDefinition
(scale 1 1 (unit distance))
)
)
(cell Sheet1_Sch
(cellType generic)
(view netListView
(viewType netlist)
(interface
)
(contents
(Instance U1
(viewRef NetlistView
(cellRef SN74LS08D
(LibraryRef COMPONENT_LIB)
)
)
(Property Code_IPC (String "SOIC127P600-14" ))
(Property Comment (String "SN74LS08D" ))
(Property (rename Component_Kind "Component Kind") (String "Standard" ))
(Property ComponentLink1Description (String "Manufacturer Link" ))
(Property ComponentLink1URL (String "http://www.ti.com/" ))
(Property ComponentLink2Description (String "Datasheet" ))
(Property ComponentLink2URL (String "http://www-s.ti.com/sc/ds/SN74LS08.pdf" ))
(Property DatasheetVersion (String "Mar-1988" ))
(Property Description (String "Quadruple 2-Input Positive-AND Gate" ))
(Property Footprint (String "D014_N" ))
(Property LatestRevisionDate (String "13-Apr-2006" ))
(Property LatestRevisionNote (String "IPC-7351 Footprint Added." ))
(Property (rename Library_Name "Library Name") (String "TI Logic Gate 2.IntLib" ))
(Property (rename Library_Reference "Library Reference") (String "SN74LS08D" ))
(Property PackageDescription (String "14-Pin Small Outline Integrated Circuit 1.27 mm Pitch" ))
(Property PackageReference (String "D014" ))
(Property PackageVersion (String "Jan-1998" ))
(Property PCB3D (String "D014" ))
(Property Published (String "8-Jun-2000" ))
(Property Publisher (String "Altium Limited" ))
(Property (rename Signal_Integrity "Signal Integrity") (String "SN74LS08D" ))
(Property Simulation (String "SN74LS08" ))
(Property Footprint (String "D014_N" ))
(Property Description (String "Quadruple 2-Input Positive-AND Gate" ))
(Property UniqueId (String "\YSMCURXJ" ))
(Property PhysicalPath (String "Sheet1" ))
(Property ChannelOffset (String "0" ))
)
(Instance U2
(viewRef NetlistView
(cellRef SN74LS08D
(LibraryRef COMPONENT_LIB)
)
)
(Property Code_IPC (String "SOIC127P600-14" ))
(Property Comment (String "SN74LS08D" ))
(Property (rename Component_Kind "Component Kind") (String "Standard" ))
(Property ComponentLink1Description (String "Manufacturer Link" ))
(Property ComponentLink1URL (String "http://www.ti.com/" ))
(Property ComponentLink2Description (String "Datasheet" ))
(Property ComponentLink2URL (String "http://www-s.ti.com/sc/ds/SN74LS08.pdf" ))
(Property DatasheetVersion (String "Mar-1988" ))
(Property Description (String "Quadruple 2-Input Positive-AND Gate" ))
(Property Footprint (String "D014_N" ))
(Property LatestRevisionDate (String "13-Apr-2006" ))
(Property LatestRevisionNote (String "IPC-7351 Footprint Added." ))
(Property (rename Library_Name "Library Name") (String "TI Logic Gate 2.IntLib" ))
(Property (rename Library_Reference "Library Reference") (String "SN74LS08D" ))
(Property PackageDescription (String "14-Pin Small Outline Integrated Circuit 1.27 mm Pitch" ))
(Property PackageReference (String "D014" ))
(Property PackageVersion (String "Jan-1998" ))
(Property PCB3D (String "D014" ))
(Property Published (String "8-Jun-2000" ))
(Property Publisher (String "Altium Limited" ))
(Property (rename Signal_Integrity "Signal Integrity") (String "SN74LS08D" ))
(Property Simulation (String "SN74LS08" ))
(Property Footprint (String "D014_N" ))
(Property Description (String "Quadruple 2-Input Positive-AND Gate" ))
(Property UniqueId (String "\JVOOYUTG" ))
(Property PhysicalPath (String "Sheet1" ))
(Property ChannelOffset (String "1" ))
)
(Instance U3
(viewRef NetlistView
(cellRef SN74LS32D
(LibraryRef COMPONENT_LIB)
)
)
(Property Code_IPC (String "SOIC127P600-14" ))
(Property Comment (String "SN74LS32D" ))
(Property (rename Component_Kind "Component Kind") (String "Standard" ))
(Property ComponentLink1Description (String "Manufacturer Link" ))
(Property ComponentLink1URL (String "http://www.ti.com/" ))
(Property ComponentLink2Description (String "Datasheet" ))
(Property ComponentLink2URL (String "http://www-s.ti.com/sc/ds/sn74ls32.pdf" ))
(Property DatasheetVersion (String "Mar-1988" ))
(Property Description (String "Quadruple 2-Input Positive-OR Gate" ))
(Property Footprint (String "D014_N" ))
(Property LatestRevisionDate (String "13-Apr-2006" ))
(Property LatestRevisionNote (String "IPC-7351 Footprint Added." ))
(Property (rename Library_Name "Library Name") (String "TI Logic Gate 2.IntLib" ))
(Property (rename Library_Reference "Library Reference") (String "SN74LS32D" ))
(Property PackageDescription (String "14-Pin Small Outline Integrated Circuit 1.27 mm Pitch" ))
(Property PackageReference (String "D014" ))
(Property PackageVersion (String "Jan-1998" ))
(Property PCB3D (String "D014" ))
(Property Published (String "8-Jun-2000" ))
(Property Publisher (String "Altium Limited" ))
(Property (rename Signal_Integrity "Signal Integrity") (String "SN74LS32D" ))
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