fpga_project1.prjfpg

altium designer09设计教程+原理图+PCB实例

[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
TimestampOutput=0
SeparateFolders=0
PinSwapBy_Netlabel=1
PinSwapBy_Pin=1
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AppendSheetNumberToLocalNets=0
DefaultConfiguration=
UserID=0xFFFFFFFF
DefaultPcbProtel=1
DefaultPcbPcad=0
ReorderDocumentsOnCompile=1
NameNetsHierarchically=1
PowerPortNamesTakePriority=0
PushECOToAnnotationFile=1
VHDL87=0
Verilog95=0

[Document1]
DocumentPath=Sheet1.Sch
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document2]
DocumentPath=C:\Program Files\Altium Designer Winter 09\Library\ON Semiconductor\ON Semi Logic Decoder Demux.IntLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document3]
DocumentPath=C:\Program Files\Altium Designer Winter 09\Library\Fairchild Semiconductor\FSC Logic Gate.IntLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document4]
DocumentPath=NB1_6_EPM7128SLC84.Constraint
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document5]
DocumentPath=Test_fpga_project1.VHDTST
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[GeneratedDocument1]
DocumentPath=ProjectOutputs\FPGA_Project1.EDF

[GeneratedDocument2]
DocumentPath=ProjectOutputs\Sheet1.VHD

[Configuration1]
Name=epm7128
ParameterCount=0
ConstraintFileCount=1
ConstraintFilePath1=NB1_6_EPM7128SLC84.Constraint

[OutputGroup1]
Name=Netlist Outputs
Description=
TargetPrinter=Microsoft XPS Document Writer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=SciCardsNetlist
OutputName1=SciCards Netlist
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=SIMetrixNetlist
OutputName2=SIMetrix
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=SIMPLISNetlist
OutputName3=SIMPLIS
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
OutputType4=ProtelNetlist
OutputName4=Protel
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
OutputType5=RacalNetlist
OutputName5=Racal Netlist
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
OutputType6=RINFNetlist
OutputName6=RINF Netlist
OutputDocumentPath6=
OutputVariantName6=
OutputDefault6=0
OutputType7=VHDL
OutputName7=VHDL File
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
Configuration7_Name1=OutputConfigurationParameter1
Configuration7_Item1=Crossprobe=False|EnableAttributes=True|Record=VHDLView|SingleFile=False
OutputType8=WireListNetlist
OutputName8=WireList Netlist
OutputDocumentPath8=
OutputVariantName8=
OutputDefault8=0
OutputType9=XSpiceNetlist
OutputName9=XSpice Netlist
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=TangoNetlist
OutputName10=Tango Netlist
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=TelesisNetlist
OutputName11=Telesis Netlist
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=Verilog
OutputName12=Verilog File
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=Protel2Netlist
OutputName13=Protel2 Netlist
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=EESofNetlist
OutputName14=EESof Netlist
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=IntergraphNetlist
OutputName15=Intergraph Netlist
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=MentorBoardStationNetlist
OutputName16=Mentor BoardStation Netlist
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=CadnetixNetlist
OutputName17=Cadnetix Netlist
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=CalayNetlist
OutputName18=Calay Netlist
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
OutputType19=EDIF
OutputName19=EDIF for PCB
OutputDocumentPath19=
OutputVariantName19=
OutputDefault19=0
Configuration19_Name1=OutputConfigurationParameter1
Configuration19_Item1=NetlistVersion=0|Record=EdifView
OutputType20=Pcad
OutputName20=Pcad for PCB
OutputDocumentPath20=
OutputVariantName20=
OutputDefault20=0
OutputType21=PCADNetlist
OutputName21=PCAD Netlist
OutputDocumentPath21=
OutputVariantName21=
OutputDefault21=0
OutputType22=PCADnltNetlist
OutputName22=PCADnlt Netlist
OutputDocumentPath22=
OutputVariantName22=
OutputDefault22=0
OutputType23=MultiWire
OutputName23=MultiWire
OutputDocumentPath23=
OutputVariantName23=
OutputDefault23=0
OutputType24=OrCadPCB2Netlist
OutputName24=Orcad/PCB2 Netlist
OutputDocumentPath24=
OutputVariantName24=
OutputDefault24=0
OutputType25=PADSNetlist
OutputName25=PADS ASCII Netlist
OutputDocumentPath25=
OutputVariantName25=
OutputDefault25=0

[OutputGroup2]
Name=Simulator Outputs
Description=
TargetPrinter=Microsoft XPS Document Writer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=AdvSimNetlist
OutputName1=Mixed Sim
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=SIMetrix_Sim
OutputName2=SIMetrix
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=SIMPLIS_Sim
OutputName3=SIMPLIS
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0

[OutputGroup3]
Name=Documentation Outputs
Description=
TargetPrinter=Microsoft XPS Document Writer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=Composite
OutputName1=Composite Drawing
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType2=Logic Analyser Print
OutputName2=Logic Analyser Prints
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType3=OpenBus Print
OutputName3=OpenBus Prints
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType4=PCB 3D Print
OutputName4=PCB 3D Prints
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1