fpga_project1.edf

altium designer09设计教程+原理图+PCB实例

            (Property ComponentLink1Description (String "Manufacturer Link" ))
            (Property ComponentLink1URL (String "http://www.fairchildsemi.com/" ))
            (Property ComponentLink2Description (String "Datasheet" ))
            (Property ComponentLink2URL (String "http://www.fairchildsemi.com/ds/74%2F74AC08.pdf" ))
            (Property DatasheetVersion (String "Nov-1999" ))
            (Property Description (String "Quad 2-Input AND Gate" ))
            (Property Footprint (String "N14A" ))
            (Property LatestRevisionDate (String "04-Mar-2005" ))
            (Property LatestRevisionNote (String "Stylized 3D Model Added." ))
            (Property (rename Library_Name "Library Name") (String "FSC Logic Gate.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "74AC08PC" ))
            (Property PackageDescription (String "DIP; 14 Leads; Row Spacing 7.62 mm; Pitch 2.54 mm" ))
            (Property PackageReference (String "N14A" ))
            (Property PackageVersion (String "2000" ))
            (Property PCB3D (String "N14A" ))
            (Property Published (String "17-Jul-2002" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "74AC08PC" ))
            (Property Simulation (String "FSC_74LS08" ))
            (Property Footprint (String "N14A" ))
            (Property Description (String "Quad 2-Input AND Gate" ))
            (Property UniqueId (String "\OYIHQNWW" ))
            (Property PhysicalPath (String "Sheet1" ))
            (Property ChannelOffset (String "1" ))
          )
          (Instance U3
            (viewRef NetlistView
              (cellRef &74AC32MTC
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "74AC32MTC" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property ComponentLink1Description (String "Manufacturer Link" ))
            (Property ComponentLink1URL (String "http://www.fairchildsemi.com/" ))
            (Property ComponentLink2Description (String "Datasheet" ))
            (Property ComponentLink2URL (String "http://www.fairchildsemi.com/ds/74%2F74AC32.pdf" ))
            (Property DatasheetVersion (String "Nov-1999" ))
            (Property Description (String "Quad 2-Input OR Gate" ))
            (Property Footprint (String "MTC14" ))
            (Property LatestRevisionDate (String "04-Mar-2005" ))
            (Property LatestRevisionNote (String "Stylized 3D Model Added." ))
            (Property (rename Library_Name "Library Name") (String "FSC Logic Gate.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "74AC32MTC" ))
            (Property PackageDescription (String "Shrink Small Outline; 14 Leads; Body Width 4.4 mm; Pitch 0.65 mm" ))
            (Property PackageReference (String "MTC14" ))
            (Property PackageVersion (String "Aug-1999" ))
            (Property PCB3D (String "MTC14" ))
            (Property Published (String "17-Jul-2002" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "74AC32MTC" ))
            (Property Simulation (String "FSC_74LS32" ))
            (Property Footprint (String "MTC14" ))
            (Property Description (String "Quad 2-Input OR Gate" ))
            (Property UniqueId (String "\VOPJGTTU" ))
            (Property PhysicalPath (String "Sheet1" ))
            (Property ChannelOffset (String "2" ))
          )
          (Instance U5
            (viewRef NetlistView
              (cellRef MC10E156FN
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "MC10E156FN" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property ComponentLink1Description (String "Manufacturer Link" ))
            (Property ComponentLink1URL (String "http://www.onsemi.com/" ))
            (Property ComponentLink2Description (String "Datasheet" ))
            (Property ComponentLink2URL (String "http://www.onsemi.com/pub/Collateral/MC10E156-D.PDF" ))
            (Property DatasheetVersion (String "1996" ))
            (Property Description (String "3-Bit 4:1 Multiplexer-Latch" ))
            (Property Footprint (String "776-02_N" ))
            (Property LatestRevisionDate (String "13-Apr-2006" ))
            (Property LatestRevisionNote (String "IPC-7351 Footprint Added." ))
            (Property (rename Library_Name "Library Name") (String "ON Semi Logic Latch.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "MC10E156FN" ))
            (Property Note (String "All VCC&VCCO pins are tied together on the die" ))
            (Property PackageDescription (String "28-Pin Leaded Chip Carrier 1.27 mm Pitch" ))
            (Property PackageReference (String "776-02" ))
            (Property PackageVersion (String "Feb-2000" ))
            (Property PCB3D (String "" ))
            (Property Published (String "15-Apr-2002" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "" ))
            (Property Simulation (String "" ))
            (Property Footprint (String "776-02_N" ))
            (Property Description (String "3-Bit 4:1 Multiplexer-Latch" ))
            (Property UniqueId (String "\HEYLTAYA" ))
            (Property PhysicalPath (String "Sheet1" ))
            (Property ChannelOffset (String "3" ))
          )
          (Net VCC
            (Joined 
                (PortRef &14 (InstanceRef U1))
                (PortRef &14 (InstanceRef U2))
                (PortRef &14 (InstanceRef U3))
            )
          )
          (Net NetU1_8
            (Joined 
                (PortRef &8 (InstanceRef U1))
                (PortRef &1 (InstanceRef U2))
                (PortRef &2 (InstanceRef U2))
                (PortRef &5 (InstanceRef U2))
                (PortRef &2 (InstanceRef U3))
            )
          )
          (Net NetU1_11
            (Joined 
                (PortRef &11 (InstanceRef U1))
            )
          )
          (Net NetU2_3
            (Joined 
                (PortRef &3 (InstanceRef U2))
                (PortRef &4 (InstanceRef U3))
            )
          )
          (Net NetU2_4
            (Joined 
                (PortRef &4 (InstanceRef U2))
            )
          )
          (Net NetU2_6
            (Joined 
                (PortRef &6 (InstanceRef U2))
                (PortRef &1 (InstanceRef U3))
                (PortRef &5 (InstanceRef U3))
            )
          )
          (Net NetU3_3
            (Joined 
                (PortRef &3 (InstanceRef U3))
                (PortRef &9 (InstanceRef U3))
                (PortRef &10 (InstanceRef U3))
            )
          )
          (Net NetU3_6
            (Joined 
                (PortRef &6 (InstanceRef U3))
                (PortRef &9 (InstanceRef U5))
            )
          )
          (Net NetU3_8
            (Joined 
                (PortRef &8 (InstanceRef U3))
                (PortRef &1 (InstanceRef U5))
                (PortRef &23 (InstanceRef U5))
            )
          )
          (Net NetU5_14
            (Joined 
                (PortRef &14 (InstanceRef U5))
            )
          )
          (Net NetU5_15
            (Joined 
                (PortRef &15 (InstanceRef U5))
            )
          )
          (Net GND
            (Joined 
                (PortRef &7 (InstanceRef U1))
                (PortRef &7 (InstanceRef U2))
                (PortRef &7 (InstanceRef U3))
            )
          )
       )
     )
   )
  )
  (design FPGA_Project1_PrjFpg
    (cellRef Sheet1_Sch
      (libraryRef SHEET_LIB)
    )
  )
)