fpga_project1.edf

altium designer09设计教程+原理图+PCB实例

(edif FPGA_Project1_PrjFpg
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap
     (keywordLevel 0)
  )
  (status
    (written
      (timeStamp 2010 5 27 17 29 25)
      (program "Altium Designer - EDIF For PCB"
        (version "1.0.0")
      )
      (author "EDIF For PCB")
    )
  )

  (library COMPONENT_LIB
    (edifLevel 0)
    (technology
      (numberDefinition
        (scale  1  1  (unit  distance))
      )
    )
    (cell (rename &54LS51DMQB "54LS51DMQB")
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port (rename &1 "1")   (direction INPUT))
          (port (rename &2 "2")   (direction INPUT))
          (port (rename &3 "3")   (direction INPUT))
          (port (rename &4 "4")   (direction INPUT))
          (port (rename &5 "5")   (direction INPUT))
          (port (rename &6 "6")   (direction OUTPUT))
          (port (rename &7 "7")   (direction INOUT))
          (port (rename &8 "8")   (direction OUTPUT))
          (port (rename &9 "9")   (direction INPUT))
          (port (rename &10 "10") (direction INPUT))
          (port (rename &11 "11") (direction INPUT))
          (port (rename &12 "12") (direction INPUT))
          (port (rename &13 "13") (direction INPUT))
          (port (rename &14 "14") (direction INOUT))
        )
      )
    )
    (cell (rename &74AC08PC "74AC08PC")
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port (rename &1 "1")   (direction INPUT))
          (port (rename &2 "2")   (direction INPUT))
          (port (rename &3 "3")   (direction OUTPUT))
          (port (rename &4 "4")   (direction INPUT))
          (port (rename &5 "5")   (direction INPUT))
          (port (rename &6 "6")   (direction OUTPUT))
          (port (rename &7 "7")   (direction INOUT))
          (port (rename &8 "8")   (direction OUTPUT))
          (port (rename &9 "9")   (direction INPUT))
          (port (rename &10 "10") (direction INPUT))
          (port (rename &11 "11") (direction OUTPUT))
          (port (rename &12 "12") (direction INPUT))
          (port (rename &13 "13") (direction INPUT))
          (port (rename &14 "14") (direction INOUT))
        )
      )
    )
    (cell (rename &74AC32MTC "74AC32MTC")
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port (rename &1 "1")   (direction INPUT))
          (port (rename &2 "2")   (direction INPUT))
          (port (rename &3 "3")   (direction OUTPUT))
          (port (rename &4 "4")   (direction INPUT))
          (port (rename &5 "5")   (direction INPUT))
          (port (rename &6 "6")   (direction OUTPUT))
          (port (rename &7 "7")   (direction INOUT))
          (port (rename &8 "8")   (direction OUTPUT))
          (port (rename &9 "9")   (direction INPUT))
          (port (rename &10 "10") (direction INPUT))
          (port (rename &11 "11") (direction OUTPUT))
          (port (rename &12 "12") (direction INPUT))
          (port (rename &13 "13") (direction INPUT))
          (port (rename &14 "14") (direction INOUT))
        )
      )
    )
    (cell MC10E156FN
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port (rename &1 "1")   (direction INOUT))
          (port (rename &2 "2")   (direction INPUT))
          (port (rename &3 "3")   (direction INPUT))
          (port (rename &4 "4")   (direction INPUT))
          (port (rename &5 "5")   (direction INPUT))
          (port (rename &6 "6")   (direction INPUT))
          (port (rename &7 "7")   (direction INPUT))
          (port (rename &8 "8")   (direction INPUT))
          (port (rename &9 "9")   (direction INPUT))
          (port (rename &10 "10") (direction INOUT))
          (port (rename &11 "11") (direction INOUT))
          (port (rename &12 "12") (direction INOUT))
          (port (rename &13 "13") (direction INOUT))
          (port (rename &14 "14") (direction INOUT))
          (port (rename &15 "15") (direction INOUT))
          (port (rename &16 "16") (direction INOUT))
          (port (rename &17 "17") (direction INOUT))
          (port (rename &18 "18") (direction INOUT))
          (port (rename &19 "19") (direction INOUT))
          (port (rename &20 "20") (direction INPUT))
          (port (rename &21 "21") (direction INPUT))
          (port (rename &22 "22") (direction INPUT))
          (port (rename &23 "23") (direction INPUT))
          (port (rename &24 "24") (direction INPUT))
          (port (rename &25 "25") (direction INPUT))
          (port (rename &26 "26") (direction INPUT))
          (port (rename &27 "27") (direction INPUT))
          (port (rename &28 "28") (direction INPUT))
        )
      )
    )
  )
  (library SHEET_LIB
    (edifLevel 0)
    (technology
      (numberDefinition
        (scale  1  1  (unit  distance))
      )
    )
    (cell Sheet1_Sch
      (cellType generic)
      (view netListView
        (viewType netlist)
        (interface
        )
        (contents
          (Instance U1
            (viewRef NetlistView
              (cellRef &54LS51DMQB
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "54LS51DMQB" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property ComponentLink1Description (String "Manufacturer Link" ))
            (Property ComponentLink1URL (String "http://www.fairchildsemi.com/" ))
            (Property DatasheetVersion (String "Mar-1998" ))
            (Property Description (String "Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate" ))
            (Property Footprint (String "J14A" ))
            (Property LatestRevisionDate (String "04-Mar-2005" ))
            (Property LatestRevisionNote (String "Stylized 3D Model Added." ))
            (Property (rename Library_Name "Library Name") (String "FSC Logic Gate.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "54LS51DMQB" ))
            (Property PackageDescription (String "DIP; 14 Leads; Row Spacing 7.62 mm; Pitch 2.54 mm" ))
            (Property PackageReference (String "J14A" ))
            (Property PackageVersion (String "2000" ))
            (Property PCB3D (String "J14A" ))
            (Property Published (String "17-Jul-2002" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "54LS51DMQB" ))
            (Property Simulation (String "" ))
            (Property Footprint (String "J14A" ))
            (Property Description (String "Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate" ))
            (Property UniqueId (String "\BMWEPBPG" ))
            (Property PhysicalPath (String "Sheet1" ))
            (Property ChannelOffset (String "0" ))
          )
          (Instance U2
            (viewRef NetlistView
              (cellRef &74AC08PC
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "74AC08PC" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))