test1.vhd

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-- VHDL Test1
-- 2010 5 27 11 21 4
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
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-- VHDL Test1
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Library IEEE;
Use     IEEE.std_logic_1164.all;

--synthesis translate_off
Library GENERIC_LIB;
Use     GENERIC_LIB.all;

--synthesis translate_on
Entity Test1 Is
  port
  (
    IN1  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=IN1
    IN2  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=IN2
    IN3  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=IN3
    IN4  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=IN4
    OUT1 : Out   STD_LOGIC                                   -- ObjectKind=Port|PrimaryId=OUT1
  );
  attribute MacroCell : boolean;

  attribute PinNum : string;
  attribute PinNum of IN2  : Signal is "4";
  attribute PinNum of IN3  : Signal is "3";
  attribute PinNum of IN4  : Signal is "2";
  attribute PinNum of OUT1 : Signal is "1";

  attribute PinNumber : string;
  attribute PinNumber of IN1 : Signal is "5";


End Test1;
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architecture structure of Test1 is
   Component AND2N1S                                         -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
      port
      (
        I0 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U1-I0
        I1 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U1-I1
        O  : out STD_LOGIC                                   -- ObjectKind=Pin|PrimaryId=U1-O
      );
   End Component;

   Component NOR2N1S                                         -- ObjectKind=Part|PrimaryId=U3|SecondaryId=1
      port
      (
        I0 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U3-I0
        I1 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U3-I1
        O  : out STD_LOGIC                                   -- ObjectKind=Pin|PrimaryId=U3-O
      );
   End Component;

   Component NOR2S                                           -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
      port
      (
        I0 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I0
        I1 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I1
        O  : out STD_LOGIC                                   -- ObjectKind=Pin|PrimaryId=U2-O
      );
   End Component;


    Signal PinSignal_U1_O : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O
    Signal PinSignal_U3_O : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_O



begin
    U3 : NOR2N1S                                             -- ObjectKind=Part|PrimaryId=U3|SecondaryId=1
      Port Map
      (
        I0 => PinSignal_U1_O,                                -- ObjectKind=Pin|PrimaryId=U3-I0
        O  => PinSignal_U3_O                                 -- ObjectKind=Pin|PrimaryId=U3-O
      );

    U2 : NOR2S                                               -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
      Port Map
      (
        I0 => IN3,                                           -- ObjectKind=Pin|PrimaryId=U2-I0
        I1 => IN4                                            -- ObjectKind=Pin|PrimaryId=U2-I1
      );

    U1 : AND2N1S                                             -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
      Port Map
      (
        I0 => IN1,                                           -- ObjectKind=Pin|PrimaryId=U1-I0
        I1 => IN2,                                           -- ObjectKind=Pin|PrimaryId=U1-I1
        O  => PinSignal_U1_O                                 -- ObjectKind=Pin|PrimaryId=U1-O
      );

    -- Signal Assignments
    ---------------------
    OUT1 <= PinSignal_U3_O; -- ObjectKind=Net|PrimaryId=NetU3_O

end structure;
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