test_fpga_16bitcounter.vhdtst

altium designer09设计教程+原理图+PCB实例

------------------------------------------------------------
-- VHDL Testbench for fpga_16bitcounter
-- 2010 5 27 14 44 23
-- Created by "EditVHDL"
-- "Copyright (c) 2002 Altium Limited"
------------------------------------------------------------

Library IEEE;
Use     IEEE.std_logic_1164.all;
Use     IEEE.std_logic_textio.all;
Use     STD.textio.all;
------------------------------------------------------------

------------------------------------------------------------
entity Testfpga_16bitcounter is
end Testfpga_16bitcounter;
------------------------------------------------------------

------------------------------------------------------------
architecture stimulus of Testfpga_16bitcounter is
    file RESULTS: TEXT open WRITE_MODE is "results.txt";
    procedure WRITE_RESULTS(
    ) is
        variable l_out : line;
    begin
        write(l_out, now, right, 15);
        writeline(RESULTS, l_out);
    end procedure;

    component fpga_16bitcounter
        port (
        );
    end component;


begin
    DUT:fpga_16bitcounter port map (
    );

    STIMULUS0:process
    begin
        -- insert stimulus here  
        wait;
    end process;

    WRITE_RESULTS(
    );

end architecture;
------------------------------------------------------------

------------------------------------------------------------