pcb_project1.prjpcb

altium designer09设计教程+原理图+PCB实例

[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
TimestampOutput=0
SeparateFolders=0
PinSwapBy_Netlabel=1
PinSwapBy_Pin=1
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AppendSheetNumberToLocalNets=0
DefaultConfiguration=
UserID=0xFFFFFFFF
DefaultPcbProtel=1
DefaultPcbPcad=0
ReorderDocumentsOnCompile=1
NameNetsHierarchically=0
PowerPortNamesTakePriority=0
PushECOToAnnotationFile=1

[Document1]
DocumentPath=PCB图.PCBDOC
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document2]
DocumentPath=原理图.SCHDOC
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[GeneratedDocument1]
DocumentPath=PCB_Project1.sdf

[GeneratedDocument2]
DocumentPath=PCB图.PCBDOC.htm

[Generic_SignalIntegritySimulation]
SignalIntegrityInitialised=-1
TrackImpedance=100
TrackLength=20000000
UseManhattan=-1
UseSupplyNetsRules=-1
SupplyNetsCount=0
UseStimulusRules=-1
StimKind=1
StimLevel=0
StimStartTime=1E-8
StimStopTime=6E-8
StimPeriodTime=1E-7

[Generic_SignalIntegrityPanelSetup]
TerminationName0=No Termination
TerminationEnabled0=True
TerminationSweeps0=1
TerminationName1=Serial Res
TerminationEnabled1=False
TerminationSweeps1=10
TerminationName2=Parallel Res to VCC
TerminationEnabled2=False
TerminationSweeps2=10
TerminationName3=Parallel Res to GND
TerminationEnabled3=False
TerminationSweeps3=10
TerminationName4=Parallel Res to VCC & GND
TerminationEnabled4=False
TerminationSweeps4=10
TerminationName5=Parallel Cap to GND
TerminationEnabled5=False
TerminationSweeps5=10
TerminationName6=Res and Cap to GND
TerminationEnabled6=False
TerminationSweeps6=10
TerminationName7=Parallel Schottky Diodes
TerminationEnabled7=False
TerminationSweeps7=10
TerminationMinR10=0
TerminationMaxR10=0
TerminationPrefR10=0
TerminationMinR20=0
TerminationMaxR20=0
TerminationPrefR20=0
TerminationMinC0=0
TerminationMaxC0=0
TerminationPrefC0=0
TerminationVCC0=0
TerminationMinR11=25
TerminationMaxR11=150
TerminationPrefR11=47
TerminationMinR21=0
TerminationMaxR21=0
TerminationPrefR21=0
TerminationMinC1=0
TerminationMaxC1=0
TerminationPrefC1=0
TerminationVCC1=0
TerminationMinR12=50
TerminationMaxR12=200
TerminationPrefR12=100
TerminationMinR22=0
TerminationMaxR22=0
TerminationPrefR22=0
TerminationMinC2=0
TerminationMaxC2=0
TerminationPrefC2=0
TerminationVCC2=5
TerminationMinR13=0
TerminationMaxR13=0
TerminationPrefR13=0
TerminationMinR23=50
TerminationMaxR23=200
TerminationPrefR23=100
TerminationMinC3=0
TerminationMaxC3=0
TerminationPrefC3=0
TerminationVCC3=0
TerminationMinR14=50
TerminationMaxR14=200
TerminationPrefR14=100
TerminationMinR24=50
TerminationMaxR24=200
TerminationPrefR24=100
TerminationMinC4=0
TerminationMaxC4=0
TerminationPrefC4=0
TerminationVCC4=5
TerminationMinR15=0
TerminationMaxR15=0
TerminationPrefR15=0
TerminationMinR25=0
TerminationMaxR25=0
TerminationPrefR25=0
TerminationMinC5=2.35E-11
TerminationMaxC5=9.4E-11
TerminationPrefC5=4.7E-11
TerminationVCC5=0
TerminationMinR16=0
TerminationMaxR16=0
TerminationPrefR16=0
TerminationMinR26=34
TerminationMaxR26=136
TerminationPrefR26=68
TerminationMinC6=5E-11
TerminationMaxC6=2E-10
TerminationPrefC6=1E-10
TerminationVCC6=0
TerminationMinR17=0
TerminationMaxR17=0
TerminationPrefR17=0
TerminationMinR27=0
TerminationMaxR27=0
TerminationPrefR27=0
TerminationMinC7=0
TerminationMaxC7=0
TerminationPrefC7=0
TerminationVCC7=5

[OutputGroup1]
Name=Netlist Outputs
Description=
TargetPrinter=Microsoft XPS Document Writer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=EDIF
OutputName1=EDIF for PCB
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=MultiWire
OutputName2=MultiWire
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=Pcad
OutputName3=Pcad for PCB
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
OutputType4=ProtelNetlist
OutputName4=Protel
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
OutputType5=Verilog
OutputName5=Verilog File
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
OutputType6=VHDL
OutputName6=VHDL File
OutputDocumentPath6=
OutputVariantName6=
OutputDefault6=0
OutputType7=XSpiceNetlist
OutputName7=XSpice Netlist
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
OutputType8=CadnetixNetlist
OutputName8=Cadnetix Netlist
OutputDocumentPath8=
OutputVariantName8=
OutputDefault8=0
OutputType9=CalayNetlist
OutputName9=Calay Netlist
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=EESofNetlist
OutputName10=EESof Netlist
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=IntergraphNetlist
OutputName11=Intergraph Netlist
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=MentorBoardStationNetlist
OutputName12=Mentor BoardStation Netlist
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=OrCadPCB2Netlist
OutputName13=Orcad/PCB2 Netlist
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=PADSNetlist
OutputName14=PADS ASCII Netlist
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=PCADNetlist
OutputName15=PCAD Netlist
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=PCADnltNetlist
OutputName16=PCADnlt Netlist
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=Protel2Netlist
OutputName17=Protel2 Netlist
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=RacalNetlist
OutputName18=Racal Netlist
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
OutputType19=RINFNetlist
OutputName19=RINF Netlist
OutputDocumentPath19=
OutputVariantName19=
OutputDefault19=0
OutputType20=SciCardsNetlist
OutputName20=SciCards Netlist
OutputDocumentPath20=
OutputVariantName20=
OutputDefault20=0
OutputType21=SIMetrixNetlist
OutputName21=SIMetrix
OutputDocumentPath21=
OutputVariantName21=
OutputDefault21=0
OutputType22=SIMPLISNetlist
OutputName22=SIMPLIS
OutputDocumentPath22=
OutputVariantName22=
OutputDefault22=0
OutputType23=TangoNetlist
OutputName23=Tango Netlist
OutputDocumentPath23=
OutputVariantName23=
OutputDefault23=0
OutputType24=TelesisNetlist
OutputName24=Telesis Netlist
OutputDocumentPath24=
OutputVariantName24=
OutputDefault24=0
OutputType25=WireListNetlist
OutputName25=WireList Netlist
OutputDocumentPath25=
OutputVariantName25=
OutputDefault25=0

[OutputGroup2]
Name=Simulator Outputs
Description=
TargetPrinter=Microsoft XPS Document Writer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=AdvSimNetlist
OutputName1=Mixed Sim