option.inc

s3c24a0固件测试代码 ? ? ? ? ?啊

;===========================================
; NAME: OPTION.A
; DESC: Configuration options for .S files
; HISTORY:
; 03.11.2003: ver 0.0
;===========================================

;Start address of each stacks,
_STACK_BASEADDRESS	EQU 0x13ff8000
_MMUTT_STARTADDRESS	EQU 0x13ff8000
_ISR_STARTADDRESS	EQU 0x13ffff00

	GBLL 	USE_MAIN 
USE_MAIN	SETL 	{TRUE}

	GBLL 	MPLL_ON_START  
MPLL_ON_START	SETL 	{FALSE}

	GBLL 	UPLL_ON_START  
UPLL_ON_START	SETL 	{FALSE}

	GBLL 	VECTOR_MODE  
VECTOR_MODE	SETL 	{FALSE}

	GBLA	ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH	SETA	16	

	GBLA    SROM_BW_DW1
SROM_BW_DW1	SETA    16

	GBLA    SROM_BW_DW2
SROM_BW_DW2	SETA    16

	GBLA	SROM_B2_CS
SROM_B2_CS		SETA	0	

	GBLA	FCLK
FCLK		SETA	84000000

    [	FCLK = 50000000	
M_MDIV	EQU	42	;Fin=12.0MHz Fout=50.0MHz
M_PDIV	EQU	1
M_SDIV	EQU	2
    ]

    [	FCLK = 56000000	
M_MDIV	EQU	48	;Fin=12.0MHz Fout=56.0MHz
M_PDIV	EQU	1
M_SDIV	EQU	2
    ]

    [	FCLK = 67000000	
M_MDIV	EQU	59	;Fin=12.0MHz Fout=67.0MHz
M_PDIV	EQU	1
M_SDIV	EQU	2
    ]

    [	FCLK = 79000000	
M_MDIV	EQU	71	;Fin=12.0MHz Fout=79.0MHz
M_PDIV	EQU	4
M_SDIV	EQU	1
    ]

    [	FCLK = 84000000	
M_MDIV	EQU	76	;Fin=12.0MHz Fout=84.0MHz
M_PDIV	EQU	4
M_SDIV	EQU	1
    ]

    [	FCLK = 90000000	
M_MDIV	EQU	82	;Fin=12.0MHz Fout=90.0MHz
M_PDIV	EQU	4
M_SDIV	EQU	1
    ]

    [	FCLK = 101000000	
M_MDIV	EQU	93	;Fin=12.0MHz Fout=101.0MHz
M_PDIV	EQU	4
M_SDIV	EQU	1
    ]

;UPLL Output Setting Value
U_MDIV	EQU	56	;Fin=12.0MHz UPLL_clk=96.0MHz
U_PDIV	EQU	2
U_SDIV	EQU	1


	END