📄 iic_s5x532.txt
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; generated by ARM C Compiler, ADS1.2 [Build 842]
; commandline [-errors .\err\iic_s5x532.err -O0 -asm -g+ -cpu 5TEJ -fs -Wd -Ec -I.\include "-IC:\Program Files\ARM\ADSv1_2\INCLUDE"]
CODE32
AREA ||.text||, CODE, READONLY
S5X532_IicInt PROC
;;;282 void __irq S5X532_IicInt(void)
;;;283 {
|L1.0|
000000 e92d503f STMFD sp!,{r0-r5,r12,lr}
;;;284 U32 iicSt,i;
;;;285
;;;286 ClearPending(BIT_IIC);
000004 e3a00680 MOV r0,#0x8000000
000008 e59f138c LDR r1,|L1.924|
00000c e5810000 STR r0,[r1,#0]
000010 e1c10000 BIC r0,r1,r0
000014 e5900010 LDR r0,[r0,#0x10]
000018 e5810010 STR r0,[r1,#0x10]
00001c e1a00001 MOV r0,r1
000020 e5900010 LDR r0,[r0,#0x10]
;;;287 iicSt = rIICSTAT;
000024 e2810644 ADD r0,r1,#0x4400000
000028 e5900004 LDR r0,[r0,#4]
00002c e1a05000 MOV r5,r0
;;;288 rINTMSK |= BIT_IIC;
000030 e1a00001 MOV r0,r1
000034 e5900008 LDR r0,[r0,#8]
000038 e3800680 ORR r0,r0,#0x8000000
00003c e5810008 STR r0,[r1,#8]
;;;289
;;;290 if(iicSt & 0x8){} //When bus arbitration is failed.
000040 e1a00000 NOP
;;;291 if(iicSt & 0x4){} //When a slave address is matched with IICADD
000044 e1a00000 NOP
;;;292 if(iicSt & 0x2){} //When a slave address is 0000000b
000048 e1a00000 NOP
;;;293 if(iicSt & 0x1){} //When ACK isn't received
00004c e1a00000 NOP
;;;294
;;;295 switch(_iicMode)
000050 e59f0348 LDR r0,|L1.928|
000054 e5900000 LDR r0,[r0,#0] ; _iicMode
000058 e3500001 CMP r0,#1
00005c 0a000033 BEQ |L1.304|
000060 e3500003 CMP r0,#3
000064 0a000002 BEQ |L1.116|
000068 e3500004 CMP r0,#4
00006c 1a000075 BNE |L1.584|
000070 ea000051 B |L1.444|
;;;296 {
;;;297 case RDDATA:
;;;298 if((_iicDataCount--)==0)
|L1.116|
000074 e59f0328 LDR r0,|L1.932|
000078 e5900000 LDR r0,[r0,#0] ; _iicDataCount
00007c e2401001 SUB r1,r0,#1
000080 e59f031c LDR r0,|L1.932|
000084 e5902000 LDR r2,[r0,#0] ; _iicDataCount
000088 e5801000 STR r1,[r0,#0] ; _iicDataCount
00008c e3520000 CMP r2,#0
000090 1a000011 BNE |L1.220|
;;;299 {
;;;300 _iicData[_iicPt++] = rIICDS;
000094 e59f030c LDR r0,|L1.936|
000098 e590100c LDR r1,[r0,#0xc]
00009c e59f0308 LDR r0,|L1.940|
0000a0 e5900000 LDR r0,[r0,#0] ; _iicPt
0000a4 e2802001 ADD r2,r0,#1
0000a8 e59f32fc LDR r3,|L1.940|
0000ac e5832000 STR r2,[r3,#0] ; _iicPt
0000b0 e59f22f8 LDR r2,|L1.944|
0000b4 e7c21000 STRB r1,[r2,r0]
;;;301
;;;302 rIICSTAT = 0x90; //Stop MasRx condition
0000b8 e3a00090 MOV r0,#0x90
0000bc e59f12e4 LDR r1,|L1.936|
0000c0 e5810004 STR r0,[r1,#4]
;;;303 rIICCON = 0xef; //Resumes IIC operation.
0000c4 e3a000ef MOV r0,#0xef
0000c8 e1c11000 BIC r1,r1,r0
0000cc e5810000 STR r0,[r1,#0]
;;;304 Delay(2); //Wait until stop condtion is in effect., Too long time... # need the time 2440:Delay(1), 24A0: Delay(2)
0000d0 e3a00002 MOV r0,#2
0000d4 ebfffffe BL Delay
;;;305 //The pending bit will not be set after issuing stop condition.
;;;306 break;
0000d8 ea00005b B |L1.588|
;;;307 }
;;;308 _iicData[_iicPt++] = rIICDS; //The last data has to be read with no ack.
|L1.220|
0000dc e59f02c4 LDR r0,|L1.936|
0000e0 e590100c LDR r1,[r0,#0xc]
0000e4 e59f02c0 LDR r0,|L1.940|
0000e8 e5900000 LDR r0,[r0,#0] ; _iicPt
0000ec e2802001 ADD r2,r0,#1
0000f0 e59f32b4 LDR r3,|L1.940|
0000f4 e5832000 STR r2,[r3,#0] ; _iicPt
0000f8 e59f22b0 LDR r2,|L1.944|
0000fc e7c21000 STRB r1,[r2,r0]
;;;309
;;;310 if((_iicDataCount)==0)
000100 e59f029c LDR r0,|L1.932|
000104 e5900000 LDR r0,[r0,#0] ; _iicDataCount
000108 e3500000 CMP r0,#0
00010c 1a000003 BNE |L1.288|
;;;311 rIICCON = 0x6f; //Resumes IIC operation with NOACK in case of S5X532 Cameara
000110 e3a0006f MOV r0,#0x6f
000114 e59f128c LDR r1,|L1.936|
000118 e5810000 STR r0,[r1,#0]
00011c ea000002 B |L1.300|
;;;312 else
;;;313 rIICCON = 0xef; //Resumes IIC operation with ACK
|L1.288|
000120 e3a000ef MOV r0,#0xef
000124 e59f127c LDR r1,|L1.936|
000128 e5810000 STR r0,[r1,#0]
;;;314 break;
|L1.300|
00012c ea000046 B |L1.588|
;;;315
;;;316 case WRDATA:
;;;317 if((_iicDataCount--)==0)
|L1.304|
000130 e59f026c LDR r0,|L1.932|
000134 e5900000 LDR r0,[r0,#0] ; _iicDataCount
000138 e2401001 SUB r1,r0,#1
00013c e59f0260 LDR r0,|L1.932|
000140 e5902000 LDR r2,[r0,#0] ; _iicDataCount
000144 e5801000 STR r1,[r0,#0] ; _iicDataCount
000148 e3520000 CMP r2,#0
00014c 1a000008 BNE |L1.372|
;;;318 {
;;;319 rIICSTAT = 0xd0; //stop MasTx condition
000150 e3a000d0 MOV r0,#0xd0
000154 e59f124c LDR r1,|L1.936|
000158 e5810004 STR r0,[r1,#4]
;;;320 rIICCON = 0xef; //resumes IIC operation.
00015c e3a000ef MOV r0,#0xef
000160 e1c11000 BIC r1,r1,r0
000164 e5810000 STR r0,[r1,#0]
;;;321 Delay(2); //wait until stop condtion is in effect. # need the time 2440:Delay(1), 24A0: Delay(2)
000168 e3a00002 MOV r0,#2
00016c ebfffffe BL Delay
;;;322 //The pending bit will not be set after issuing stop condition.
;;;323 break;
000170 ea000035 B |L1.588|
;;;324 }
;;;325 rIICDS = _iicData[_iicPt++]; //_iicData[0] has dummy.
|L1.372|
000174 e59f0230 LDR r0,|L1.940|
000178 e5900000 LDR r0,[r0,#0] ; _iicPt
00017c e2801001 ADD r1,r0,#1
000180 e59f2224 LDR r2,|L1.940|
000184 e5821000 STR r1,[r2,#0] ; _iicPt
000188 e59f1220 LDR r1,|L1.944|
00018c e7d10000 LDRB r0,[r1,r0]
000190 e59f1210 LDR r1,|L1.936|
000194 e581000c STR r0,[r1,#0xc]
;;;326 for(i=0;i<50;i++); //for setup time until rising edge of IICSCL
000198 e3a04000 MOV r4,#0
|L1.412|
00019c e3540032 CMP r4,#0x32
0001a0 2a000001 BCS |L1.428|
0001a4 e2844001 ADD r4,r4,#1
0001a8 eafffffb B |L1.412|
;;;327 rIICCON = 0xef; //resumes IIC operation.
|L1.428|
0001ac e3a000ef MOV r0,#0xef
0001b0 e59f11f0 LDR r1,|L1.936|
0001b4 e5810000 STR r0,[r1,#0]
;;;328 break;
0001b8 ea000023 B |L1.588|
;;;329
;;;330 case SETRDADDR:
;;;331 // Uart_Printf("[S%d]",_iicDataCount);
;;;332 if((_iicDataCount--)==0)
|L1.444|
0001bc e59f01e0 LDR r0,|L1.932|
0001c0 e5900000 LDR r0,[r0,#0] ; _iicDataCount
0001c4 e2401001 SUB r1,r0,#1
0001c8 e59f01d4 LDR r0,|L1.932|
0001cc e5902000 LDR r2,[r0,#0] ; _iicDataCount
0001d0 e5801000 STR r1,[r0,#0] ; _iicDataCount
0001d4 e3520000 CMP r2,#0
0001d8 1a000008 BNE |L1.512|
;;;333 {
;;;334 rIICSTAT = 0xd0; //stop MasTx condition
0001dc e3a000d0 MOV r0,#0xd0
0001e0 e59f11c0 LDR r1,|L1.936|
0001e4 e5810004 STR r0,[r1,#4]
;;;335 rIICCON = 0xef; //resumes IIC operation.
0001e8 e3a000ef MOV r0,#0xef
0001ec e1c11000 BIC r1,r1,r0
0001f0 e5810000 STR r0,[r1,#0]
;;;336 Delay(2); //wait until stop condtion is in effect.
0001f4 e3a00002 MOV r0,#2
0001f8 ebfffffe BL Delay
;;;337
;;;338 break; //IIC operation is stopped because of IICCON[4]
0001fc ea000012 B |L1.588|
;;;339 }
;;;340 rIICDS = _iicData[_iicPt++];
|L1.512|
000200 e59f01a4 LDR r0,|L1.940|
000204 e5900000 LDR r0,[r0,#0] ; _iicPt
000208 e2801001 ADD r1,r0,#1
00020c e59f2198 LDR r2,|L1.940|
000210 e5821000 STR r1,[r2,#0] ; _iicPt
000214 e59f1194 LDR r1,|L1.944|
000218 e7d10000 LDRB r0,[r1,r0]
00021c e59f1184 LDR r1,|L1.936|
000220 e581000c STR r0,[r1,#0xc]
;;;341 for(i=0;i<50;i++); //for setup time until rising edge of IICSCL
000224 e3a04000 MOV r4,#0
|L1.552|
000228 e3540032 CMP r4,#0x32
00022c 2a000001 BCS |L1.568|
000230 e2844001 ADD r4,r4,#1
000234 eafffffb B |L1.552|
;;;342 rIICCON = 0xef; //resumes IIC operation.
|L1.568|
000238 e3a000ef MOV r0,#0xef
00023c e59f1164 LDR r1,|L1.936|
000240 e5810000 STR r0,[r1,#0]
;;;343 break;
000244 ea000000 B |L1.588|
;;;344
;;;345 default:
;;;346 break;
|L1.584|
000248 e1a00000 NOP
;;;347 }
;;;348
;;;349 rINTMSK &= ~BIT_IIC;
|L1.588|
00024c e59f0148 LDR r0,|L1.924|
000250 e5900008 LDR r0,[r0,#8]
000254 e3c00680 BIC r0,r0,#0x8000000
000258 e59f113c LDR r1,|L1.924|
00025c e5810008 STR r0,[r1,#8]
;;;350 }
000260 e8bd503f LDMFD sp!,{r0-r5,r12,lr}
000264 e25ef004 SUBS pc,lr,#4
ENDP
S5X532_Iic_Test PROC
;;;58 void S5X532_Iic_Test(void)
;;;59 {
000268 e92d4010 STMFD sp!,{r4,lr}
;;;60 int i, camclk;
;;;61
;;;62
;;;63 Uart_Printf("\n***** IIC Master Tx/Rx Test Program with S5X532 *****\n");
00026c e28f0f50 ADR r0,|L1.948|
000270 ebfffffe BL _printf
;;;64 rCLKCON |= ((1<<23)|(1<<21)); // enable camclk
000274 e3a00440 MOV r0,#0x40000000
000278 e5900020 LDR r0,[r0,#0x20]
00027c e38008a0 ORR r0,r0,#0xa00000
000280 e3a01440 MOV r1,#0x40000000
000284 e5810020 STR r0,[r1,#0x20]
;;;65
;;;66 CamReset(1); // s5x532 must do this.. CAMRST : ---|_____|---
000288 e3a00001 MOV r0,#1
00028c ebfffffe BL CamReset
;;;67
;;;68 Delay(1000); // ready time of s5x433, s5x532 IIC interface. needed...
000290 e3a00ffa MOV r0,#0x3e8
000294 ebfffffe BL Delay
;;;69
;;;70 // Selecting cam clock
;;;71 Uart_Printf("Input Camera Clock\n");
000298 e28f0f53 ADR r0,|L1.1004|
00029c ebfffffe BL _printf
;;;72 Uart_Printf("0:48Mhz, 1:24Mhz, 2:16Mhz, 3:12Mhz, 4:9.6Mhz\n");
0002a0 e28f0f56 ADR r0,|L1.1024|
0002a4 ebfffffe BL _printf
;;;73 i = Uart_GetIntNum();
0002a8 ebfffffe BL Uart_GetIntNum
0002ac e1a04000 MOV r4,r0
;;;74 SetCAMClockDivider(i); //Set Camera Clock
0002b0 e1a00004 MOV r0,r4
0002b4 ebfffffe BL SetCAMClockDivider
;;;75
;;;76
;;;77 pISR_IIC = (unsigned)S5X532_IicInt;
0002b8 e59f0170 LDR r0,|L1.1072|
0002bc e59f1170 LDR r1,|L1.1076|
0002c0 e5810f8c STR r0,[r1,#0xf8c]
;;;78 rINTMSK &= ~(BIT_IIC);
0002c4 e59f00d0 LDR r0,|L1.924|
0002c8 e5900008 LDR r0,[r0,#8]
0002cc e3c00680 BIC r0,r0,#0x8000000
0002d0 e59f10c4 LDR r1,|L1.924|
0002d4 e5810008 STR r0,[r1,#8]
;;;79
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