📄 strata16.txt
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; generated by ARM C Compiler, ADS1.2 [Build 842]
; commandline [-errors .\err\strata16.err -O0 -asm -g+ -cpu 5TEJ -fs -Wd -Ec -I.\include "-IC:\Program Files\ARM\ADSv1_2\INCLUDE"]
CODE32
AREA ||.text||, CODE, READONLY
Strata_CheckID PROC
;;;53 static int Strata_CheckID(int targetAddr)
;;;54 {
|L1.0|
000000 e92d4010 STMFD sp!,{r4,lr}
000004 e1a04000 MOV r4,r0
;;;55 _RESET();
000008 e3a000ff MOV r0,#0xff
00000c e59f1028 LDR r1,|L1.60|
000010 e5911000 LDR r1,[r1,#0] ; targetAddress
000014 e1c100b0 STRH r0,[r1,#0]
;;;56 _WR(targetAddr, 0x0090);
000018 e3a00090 MOV r0,#0x90
00001c e1c400b0 STRH r0,[r4,#0]
;;;57 Uart_Printf("Identification code=%x, Target Addr=%x\n",_RD(targetAddr), targetAddr);
000020 e1d400b0 LDRH r0,[r4,#0]
000024 e1a01000 MOV r1,r0
000028 e1a02004 MOV r2,r4
00002c e28f000c ADR r0,|L1.64|
000030 ebfffffe BL _printf
;;;58 return _RD(targetAddr); // Read Identifier Code, including lower, higher 16-bit, 8MB, Intel Strate Flash ROM
000034 e1d400b0 LDRH r0,[r4,#0]
;;;59 // targetAddress must be the beginning location of a Block Address
;;;60 }
000038 e8bd8010 LDMFD sp!,{r4,pc}
|L1.60|
00003c 00000010 DCD ||.bss$2|| + 16
|L1.64|
000040 6e656449 DCB "Iden"
000044 69666974 DCB "tifi"
000048 69746163 DCB "cati"
00004c 63206e6f DCB "on c"
000050 3d65646f DCB "ode="
000054 202c7825 DCB "%x, "
000058 67726154 DCB "Targ"
00005c 41207465 DCB "et A"
000060 3d726464 DCB "ddr="
000064 000a7825 DCB "%x\n\0"
ENDP
Strata_CheckDevice PROC
;;;64 static int Strata_CheckDevice(int targetAddr)
;;;65 {
000068 e92d4010 STMFD sp!,{r4,lr}
00006c e1a04000 MOV r4,r0
;;;66 //_RESET();
;;;67 _WR(targetAddr, 0x0090);
000070 e3a00090 MOV r0,#0x90
000074 e1c400b0 STRH r0,[r4,#0]
;;;68 Uart_Printf("Identification code=%x\n",_RD(targetAddr+0x2));
000078 e1d400b2 LDRH r0,[r4,#2]
00007c e1a01000 MOV r1,r0
000080 e28f0008 ADR r0,|L1.144|
000084 ebfffffe BL _printf
;;;69 return _RD(targetAddr+0x2); // Read Device Code, including lower, higher 16-bit, 8MB, Intel Strate Flash ROM
000088 e1d400b2 LDRH r0,[r4,#2]
;;;70 // targetAddress must be the beginning location of a Block Address
;;;71 }
00008c e8bd8010 LDMFD sp!,{r4,pc}
|L1.144|
000090 6e656449 DCB "Iden"
000094 69666974 DCB "tifi"
000098 69746163 DCB "cati"
00009c 63206e6f DCB "on c"
0000a0 3d65646f DCB "ode="
0000a4 000a7825 DCB "%x\n\0"
ENDP
Strata_CheckBlockLock PROC
;;;75 static int Strata_CheckBlockLock(int targetAddr)
;;;76 {
0000a8 e1a01000 MOV r1,r0
;;;77 //_RESET();
;;;78 _WR(targetAddr, 0x0090);
0000ac e3a00090 MOV r0,#0x90
0000b0 e1c100b0 STRH r0,[r1,#0]
;;;79 return _RD(targetAddr+0x4); // Read Block Lock configuration,
0000b4 e1d100b4 LDRH r0,[r1,#4]
;;;80 // targetAddress must be the beginning location of a Block Address
;;;81 }
0000b8 e12fff1e BX lr
ENDP
Strata_ClearBlockLock PROC
;;;85 static int Strata_ClearBlockLock(int targetAddr)
;;;86 {
0000bc e92d41f0 STMFD sp!,{r4-r8,lr}
0000c0 e1a04000 MOV r4,r0
;;;87 U32 status,ReadStatus;
;;;88 unsigned long bSR7,bSR1;
;;;89 //_RESET();
;;;90 _WR(targetAddr, 0x0060);
0000c4 e3a00060 MOV r0,#0x60
0000c8 e1c400b0 STRH r0,[r4,#0]
;;;91 _WR(targetAddr, 0x00d0);
0000cc e3a000d0 MOV r0,#0xd0
0000d0 e1c400b0 STRH r0,[r4,#0]
;;;92
;;;93 _WR(targetAddr, 0x0090);
0000d4 e3a00090 MOV r0,#0x90
0000d8 e1c400b0 STRH r0,[r4,#0]
;;;94 status=_RD(targetAddr+0x4);
0000dc e1d400b4 LDRH r0,[r4,#4]
0000e0 e1a05000 MOV r5,r0
;;;95 bSR7=status & (1<<7);
0000e4 e2057080 AND r7,r5,#0x80
;;;96 bSR1=status & (1<<1);
0000e8 e2058002 AND r8,r5,#2
;;;97
;;;98 Uart_Printf("Block status register value: %x\n",status);
0000ec e1a01005 MOV r1,r5
0000f0 e28f0080 ADR r0,|L1.376|
0000f4 ebfffffe BL _printf
;;;99
;;;100 while(bSR1)
0000f8 e1a00000 NOP
|L1.252|
0000fc e3580000 CMP r8,#0
000100 0a000008 BEQ |L1.296|
;;;101 {
;;;102 _WR(targetAddr, 0x0090);
000104 e3a00090 MOV r0,#0x90
000108 e1c400b0 STRH r0,[r4,#0]
;;;103 status=_RD(targetAddr+0x4);
00010c e1d400b4 LDRH r0,[r4,#4]
000110 e1a05000 MOV r5,r0
;;;104 bSR1=status & (1<<1);
000114 e2058002 AND r8,r5,#2
;;;105 if(!bSR1)break;
000118 e3580000 CMP r8,#0
00011c 1a000000 BNE |L1.292|
000120 ea000000 B |L1.296|
;;;106 }
|L1.292|
000124 eafffff4 B |L1.252|
;;;107
;;;108 Uart_Printf("Device is unlocked\n");
|L1.296|
000128 e28f006c ADR r0,|L1.412|
00012c ebfffffe BL _printf
;;;109
;;;110 _WR(targetAddr, 0x0070); // Read Status Register
000130 e3a00070 MOV r0,#0x70
000134 e1c400b0 STRH r0,[r4,#0]
;;;111 ReadStatus=_RD(targetAddr); // realAddr is any valid address within the device
000138 e1d460b0 LDRH r6,[r4,#0]
;;;112 bSR7=ReadStatus & (1<<7);
00013c e2067080 AND r7,r6,#0x80
;;;113 while(!bSR7 )
000140 e1a00000 NOP
|L1.324|
000144 e3570000 CMP r7,#0
000148 1a000005 BNE |L1.356|
;;;114 {
;;;115 _WR(targetAddr, 0x0070); // Read Status Register
00014c e3a00070 MOV r0,#0x70
000150 e1c400b0 STRH r0,[r4,#0]
;;;116 ReadStatus=_RD(targetAddr);
000154 e1d400b0 LDRH r0,[r4,#0]
000158 e1a06000 MOV r6,r0
;;;117 bSR7=ReadStatus & (1<<7);
00015c e2067080 AND r7,r6,#0x80
;;;118 }
000160 eafffff7 B |L1.324|
;;;119 _RESET();
|L1.356|
000164 e3a000ff MOV r0,#0xff
000168 e51f1134 LDR r1,|L1.60|
00016c e5911000 LDR r1,[r1,#0] ; targetAddress
000170 e1c100b0 STRH r0,[r1,#0]
;;;120 }
000174 e8bd81f0 LDMFD sp!,{r4-r8,pc}
|L1.376|
000178 636f6c42 DCB "Bloc"
00017c 7473206b DCB "k st"
000180 73757461 DCB "atus"
000184 67657220 DCB " reg"
000188 65747369 DCB "iste"
00018c 61762072 DCB "r va"
000190 3a65756c DCB "lue:"
000194 0a782520 DCB " %x\n"
000198 00000000 DCB "\0\0\0\0"
|L1.412|
00019c 69766544 DCB "Devi"
0001a0 69206563 DCB "ce i"
0001a4 6e752073 DCB "s un"
0001a8 6b636f6c DCB "lock"
0001ac 000a6465 DCB "ed\n\0"
ENDP
Strata_EraseSector PROC
;;;123 void Strata_EraseSector(int targetAddress)
;;;124 {
0001b0 e92d40f8 STMFD sp!,{r3-r7,lr}
0001b4 e1a04000 MOV r4,r0
;;;125 unsigned long ReadStatus;
;;;126 unsigned long bSR5; // Erase and Clear Lock-bits Status, lower 16bit, 8MB Intel Strate Flash ROM
;;;127 unsigned long bSR7; // Write State Machine Status, lower 16bit, 8MB Intel Strate Flash ROM
;;;128
;;;129 //_RESET();
;;;130 _WR(targetAddress, 0x0020); // Block Erase, First Bus Cycle, targetAddress is the address withint the block
0001b8 e3a00020 MOV r0,#0x20
0001bc e1c400b0 STRH r0,[r4,#0]
;;;131 _WR(targetAddress, 0x00d0); // Block Erase, Second Bus Cycle, targetAddress is the address withint the block
0001c0 e3a000d0 MOV r0,#0xd0
0001c4 e1c400b0 STRH r0,[r4,#0]
;;;132
;;;133 //_RESET();
;;;134 _WR(targetAddress, 0x0070); // Read Status Register, First Bus Cycle, targetAddress is any valid address within the device
0001c8 e3a00070 MOV r0,#0x70
0001cc e1c400b0 STRH r0,[r4,#0]
;;;135 ReadStatus=_RD(targetAddress); // Read Status Register, Second Bus Cycle, targetAddress is any valid address within the device
0001d0 e1d400b0 LDRH r0,[r4,#0]
0001d4 e1a05000 MOV r5,r0
;;;136 bSR7=ReadStatus & (1<<7); // lower 16-bit 8MB Strata
0001d8 e2056080 AND r6,r5,#0x80
;;;137 while(!bSR7)
0001dc e1a00000 NOP
|L1.480|
0001e0 e3560000 CMP r6,#0
0001e4 1a000005 BNE |L1.512|
;;;138 {
;;;139 _WR(targetAddress, 0x0070);
0001e8 e3a00070 MOV r0,#0x70
0001ec e1c400b0 STRH r0,[r4,#0]
;;;140 ReadStatus=_RD(targetAddress);
0001f0 e1d400b0 LDRH r0,[r4,#0]
0001f4 e1a05000 MOV r5,r0
;;;141 bSR7=ReadStatus & (1<<7);
0001f8 e2056080 AND r6,r5,#0x80
;;;142 }
0001fc eafffff7 B |L1.480|
;;;143
;;;144 _WR(targetAddress, 0x0070); // When the block erase is complete, status register bit SR.5 should be checked.
|L1.512|
000200 e3a00070 MOV r0,#0x70
000204 e1c400b0 STRH r0,[r4,#0]
;;;145 // If a block erase error is detected, the status register should be cleared before
;;;146 // system software attempts correct actions.
;;;147 ReadStatus=_RD(targetAddress);
000208 e1d400b0 LDRH r0,[r4,#0]
00020c e1a05000 MOV r5,r0
;;;148 bSR5=ReadStatus & (1<<5); // lower 16-bit 8MB Strata
000210 e2057020 AND r7,r5,#0x20
;;;149 if (bSR5==0)
000214 e3570000 CMP r7,#0
000218 1a000003 BNE |L1.556|
;;;150 {
;;;151 Uart_Printf("Block_%x Erase O.K. \n",targetAddress);
00021c e1a01004 MOV r1,r4
000220 e28f0024 ADR r0,|L1.588|
000224 ebfffffe BL _printf
000228 ea000004 B |L1.576|
;;;152 }
;;;153 else
;;;154 {
;;;155 //Uart_Printf("Error in Block Erasure!!\n");
;;;156 _WR(targetAddress, 0x0050); // Clear Status Register
|L1.556|
00022c e3a00050 MOV r0,#0x50
000230 e1c400b0 STRH r0,[r4,#0]
;;;157 error_erase=1; // But not major, is it casual ?
000234 e3a00001 MOV r0,#1
000238 e59f1024 LDR r1,|L1.612|
00023c e5810000 STR r0,[r1,#0] ; error_erase
;;;158 }
;;;159
;;;160 _RESET(); // write 0xffh(_RESET()) after the last opoeration to reset the device to read array mode.
|L1.576|
000240 e3a000ff MOV r0,#0xff
000244 e1c400b0 STRH r0,[r4,#0]
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