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📄 camproset.txt

📁 s3c24a0固件测试代码 ? ? ? ? ?啊 
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0002c8  e581000c          STR      r0,[r1,#0xc]
;;;122    			for(i=0;i<50;i++);                  //for setup time until rising edge of IICSCL
0002cc  e3a04000          MOV      r4,#0
                  |L1.720|
0002d0  e3540032          CMP      r4,#0x32
0002d4  2a000001          BCS      |L1.736|
0002d8  e2844001          ADD      r4,r4,#1
0002dc  eafffffb          B        |L1.720|
;;;123    				rIICCON = 0xef;                     //resumes IIC operation.
                  |L1.736|
0002e0  e3a000ef          MOV      r0,#0xef
0002e4  e59f121c          LDR      r1,|L1.1288|
0002e8  e5810000          STR      r0,[r1,#0]
;;;124    			break;
0002ec  ea000023          B        |L1.896|
;;;125    		case CAMSETRDADDR:
;;;126    			if((_CAMiicDataCount--)==0) {
                  |L1.752|
0002f0  e59f020c          LDR      r0,|L1.1284|
0002f4  e5900000          LDR      r0,[r0,#0]  ; _CAMiicDataCount
0002f8  e2401001          SUB      r1,r0,#1
0002fc  e59f0200          LDR      r0,|L1.1284|
000300  e5902000          LDR      r2,[r0,#0]  ; _CAMiicDataCount
000304  e5801000          STR      r1,[r0,#0]  ; _CAMiicDataCount
000308  e3520000          CMP      r2,#0
00030c  1a000008          BNE      |L1.820|
;;;127    				rIICSTAT = 0xd0;                //stop MasTx condition 
000310  e3a000d0          MOV      r0,#0xd0
000314  e59f11ec          LDR      r1,|L1.1288|
000318  e5810004          STR      r0,[r1,#4]
;;;128    				rIICCON  = 0xef;                //resumes IIC operation.
00031c  e3a000ef          MOV      r0,#0xef
000320  e1c11000          BIC      r1,r1,r0
000324  e5810000          STR      r0,[r1,#0]
;;;129    				Delay(2);      //wait until stop condtion is in effect.
000328  e3a00002          MOV      r0,#2
00032c  ebfffffe          BL       Delay
;;;130    
;;;131    				break;                  //IIC operation is stopped because of IICCON[4]    
000330  ea000012          B        |L1.896|
;;;132    			}
;;;133    			rIICDS = _CAMiicData[_CAMiicPt++];
                  |L1.820|
000334  e59f01c0          LDR      r0,|L1.1276|
000338  e5900000          LDR      r0,[r0,#0]  ; _CAMiicPt
00033c  e2801001          ADD      r1,r0,#1
000340  e59f21b4          LDR      r2,|L1.1276|
000344  e5821000          STR      r1,[r2,#0]  ; _CAMiicPt
000348  e59f11b0          LDR      r1,|L1.1280|
00034c  e7d10000          LDRB     r0,[r1,r0]
000350  e59f11b0          LDR      r1,|L1.1288|
000354  e581000c          STR      r0,[r1,#0xc]
;;;134    			for(i=0;i<50;i++);          //for setup time until rising edge of IICSCL
000358  e3a04000          MOV      r4,#0
                  |L1.860|
00035c  e3540032          CMP      r4,#0x32
000360  2a000001          BCS      |L1.876|
000364  e2844001          ADD      r4,r4,#1
000368  eafffffb          B        |L1.860|
;;;135    				rIICCON = 0xef;             //resumes IIC operation.
                  |L1.876|
00036c  e3a000ef          MOV      r0,#0xef
000370  e59f1190          LDR      r1,|L1.1288|
000374  e5810000          STR      r0,[r1,#0]
;;;136    			break;
000378  ea000000          B        |L1.896|
;;;137    		default:
;;;138    			break;      
                  |L1.892|
00037c  e1a00000          NOP      
;;;139    	}
;;;140    
;;;141    	rINTMSK &= ~BIT_IIC;
                  |L1.896|
000380  e59f0184          LDR      r0,|L1.1292|
000384  e5900008          LDR      r0,[r0,#8]
000388  e3c00680          BIC      r0,r0,#0x8000000
00038c  e59f1178          LDR      r1,|L1.1292|
000390  e5810008          STR      r0,[r1,#8]
;;;142    }
000394  e8bd503f          LDMFD    sp!,{r0-r5,r12,lr}
000398  e25ef004          SUBS     pc,lr,#4
                          ENDP

                  Camera_WriteBlock PROC
;;;145    void Camera_WriteBlock(void)
;;;146    {
00039c  e92d4010          STMFD    sp!,{r4,lr}
;;;147       	U32 i;
;;;148    	
;;;149    	pISR_IIC = (unsigned)Cam_IICInt; 
0003a0  e59f0168          LDR      r0,|L1.1296|
0003a4  e59f1168          LDR      r1,|L1.1300|
0003a8  e5810f8c          STR      r0,[r1,#0xf8c]
;;;150    	rINTMSK &= ~(BIT_IIC);
0003ac  e59f0158          LDR      r0,|L1.1292|
0003b0  e5900008          LDR      r0,[r0,#8]
0003b4  e3c00680          BIC      r0,r0,#0x8000000
0003b8  e59f114c          LDR      r1,|L1.1292|
0003bc  e5810008          STR      r0,[r1,#8]
;;;151    
;;;152    	//Enable ACK, Prescaler IICCLK=PCLK/512, Enable interrupt, Transmit clock value Tx clock=IICCLK/16
;;;153    	rIICCON  = (1<<7) | (1<<6) | (1<<5) | (0xf);
0003c0  e3a000ef          MOV      r0,#0xef
0003c4  e2811644          ADD      r1,r1,#0x4400000
0003c8  e5810000          STR      r0,[r1,#0]
;;;154    
;;;155    	rIICADD  = 0x10;                    //24A0 slave address = [7:1]
0003cc  e3a00010          MOV      r0,#0x10
0003d0  e1c11000          BIC      r1,r1,r0
0003d4  e5810008          STR      r0,[r1,#8]
;;;156    	rIICSTAT = 0x10;                    //IIC bus data output enable(Rx/Tx)
0003d8  e3a00010          MOV      r0,#0x10
0003dc  e1c11000          BIC      r1,r1,r0
0003e0  e5810004          STR      r0,[r1,#4]
;;;157    	rIICSDADLY  = (1<<2)|(3); 			// SDAOUT has 5clock cycle delay
0003e4  e3a00007          MOV      r0,#7
0003e8  e1c11000          BIC      r1,r1,r0
0003ec  e5810010          STR      r0,[r1,#0x10]
;;;158    
;;;159    	switch(CAMTYPE) {
0003f0  e59f0120          LDR      r0,|L1.1304|
0003f4  e5900000          LDR      r0,[r0,#0]  ; CAMTYPE
0003f8  e3500000          CMP      r0,#0
0003fc  0a000004          BEQ      |L1.1044|
000400  e3500001          CMP      r0,#1
000404  0a000012          BEQ      |L1.1108|
000408  e3500003          CMP      r0,#3
00040c  1a000030          BNE      |L1.1236|
000410  ea00001f          B        |L1.1172|
;;;160    		case CAM_OV7620:
;;;161    			for(i=0; i<(sizeof(Ov7620_YCbCr8bit)/2); i++)
                  |L1.1044|
000414  e3a04000          MOV      r4,#0
                  |L1.1048|
000418  e3540041          CMP      r4,#0x41
00041c  2a00000b          BCS      |L1.1104|
000420  ea000001          B        |L1.1068|
                  |L1.1060|
000424  e2844001          ADD      r4,r4,#1
000428  eafffffa          B        |L1.1048|
;;;162    				Wr_CamIIC(CAMIICID, Ov7620_YCbCr8bit[i][0], Ov7620_YCbCr8bit[i][1]);
                  |L1.1068|
00042c  e59f00e8          LDR      r0,|L1.1308|
000430  e0800084          ADD      r0,r0,r4,LSL #1
000434  e5d02001          LDRB     r2,[r0,#1]
000438  e59f00dc          LDR      r0,|L1.1308|
00043c  e7d01084          LDRB     r1,[r0,r4,LSL #1]
000440  e59f00d8          LDR      r0,|L1.1312|
000444  e5900000          LDR      r0,[r0,#0]  ; CAMIICID
000448  ebfffffe          BL       Wr_CamIIC
00044c  eafffff4          B        |L1.1060|
;;;163    			break;
                  |L1.1104|
000450  ea000020          B        |L1.1240|
;;;164    		case CAM_OV7620_16:
;;;165    			for(i=0; i<(sizeof(Ov7620_Yuv16bit)/2); i++)
                  |L1.1108|
000454  e3a04000          MOV      r4,#0
                  |L1.1112|
000458  e354001a          CMP      r4,#0x1a
00045c  2a00000b          BCS      |L1.1168|
000460  ea000001          B        |L1.1132|
                  |L1.1124|
000464  e2844001          ADD      r4,r4,#1
000468  eafffffa          B        |L1.1112|
;;;166    				Wr_CamIIC(CAMIICID, Ov7620_Yuv16bit[i][0], Ov7620_Yuv16bit[i][1]);
                  |L1.1132|
00046c  e59f00b0          LDR      r0,|L1.1316|
000470  e0800084          ADD      r0,r0,r4,LSL #1
000474  e5d02001          LDRB     r2,[r0,#1]
000478  e59f00a4          LDR      r0,|L1.1316|
00047c  e7d01084          LDRB     r1,[r0,r4,LSL #1]
000480  e59f0098          LDR      r0,|L1.1312|
000484  e5900000          LDR      r0,[r0,#0]  ; CAMIICID
000488  ebfffffe          BL       Wr_CamIIC
00048c  eafffff4          B        |L1.1124|
;;;167    			break;			
                  |L1.1168|
000490  ea000010          B        |L1.1240|
;;;168    		case CAM_S5X532:
;;;169    			for(i=0; i<(sizeof(S5X532_YCbCr8bit_TV)/2); i++)
                  |L1.1172|
000494  e3a04000          MOV      r4,#0
                  |L1.1176|
000498  e354005d          CMP      r4,#0x5d
00049c  2a00000b          BCS      |L1.1232|
0004a0  ea000001          B        |L1.1196|
                  |L1.1188|
0004a4  e2844001          ADD      r4,r4,#1
0004a8  eafffffa          B        |L1.1176|
;;;170    				Wr_CamIIC(CAMIICID, S5X532_YCbCr8bit_TV[i][0], S5X532_YCbCr8bit_TV[i][1]);
                  |L1.1196|
0004ac  e59f0074          LDR      r0,|L1.1320|
0004b0  e0800084          ADD      r0,r0,r4,LSL #1
0004b4  e5d02001          LDRB     r2,[r0,#1]
0004b8  e59f0068          LDR      r0,|L1.1320|
0004bc  e7d01084          LDRB     r1,[r0,r4,LSL #1]
0004c0  e59f0058          LDR      r0,|L1.1312|
0004c4  e5900000          LDR      r0,[r0,#0]  ; CAMIICID
0004c8  ebfffffe          BL       Wr_CamIIC
0004cc  eafffff4          B        |L1.1188|
;;;171    			break;
                  |L1.1232|
0004d0  ea000000          B        |L1.1240|
;;;172    		default:
;;;173    			break;
                  |L1.1236|
0004d4  e1a00000          NOP      
;;;174    	}			
;;;175    			
;;;176           Uart_Printf("\nBlock TX Ended...\n");	
                  |L1.1240|
0004d8  e28f004c          ADR      r0,|L1.1324|
0004dc  ebfffffe          BL       _printf
;;;177    	rINTMSK |= BIT_IIC;
0004e0  e59f0024          LDR      r0,|L1.1292|
0004e4  e5900008          LDR      r0,[r0,#8]
0004e8  e3800680          ORR      r0,r0,#0x8000000
0004ec  e59f1018          LDR      r1,|L1.1292|
0004f0  e5810008          STR      r0,[r1,#8]
;;;178    
;;;179    }
0004f4  e8bd8010          LDMFD    sp!,{r4,pc}
                  |L1.1272|
0004f8  00000124          DCD      ||.bss$2|| + 292
                  |L1.1276|
0004fc  00000128          DCD      ||.bss$2|| + 296
                  |L1.1280|
000500  00000100          DCD      ||.bss$2|| + 256
                  |L1.1284|
000504  00000120          DCD      ||.bss$2|| + 288
                  |L1.1288|
000508  44600000          DCD      0x44600000
                  |L1.1292|
00050c  40200000          DCD      0x40200000
                  |L1.1296|
000510  00000000          DCD      Cam_IICInt
                  |L1.1300|
000514  13fff000          DCD      0x13fff000
                  |L1.1304|
000518  00000000          DCD      CAMTYPE
                  |L1.1308|
00051c  00000034          DCD      ||.constdata$1|| + 52
                  |L1.1312|
000520  00000000          DCD      CAMIICID
                  |L1.1316|
000524  00000000          DCD      ||.constdata$1||
                  |L1.1320|
000528  000000b6          DCD      ||.constdata$1|| + 182
                  |L1.1324|
00052c  6f6c420a          DCB      "\nBlo"
000530  54206b63          DCB      "ck T"
000534  6e452058          DCB      "X En"
000538  2e646564          DCB      "ded."
00053c  000a2e2e          DCB      "..\n\0"
                          ENDP

                  Camera_ReadBlock PROC
;;;181    void Camera_ReadBlock(void)
;;;182    {
000540  e92d4010          STMFD    sp!,{r4,lr}
;;;183    	U32 i;
;;;184    	static U8 rdata[256];
;;;185    
;;;186    	pISR_IIC = (unsigned)Cam_IICInt; 
000544  e51f003c          LDR      r0,|L1.1296|
000548  e51f103c          LDR      r1,|L1.1300|
00054c  e5810f8c          STR      r0,[r1,#0xf8c]
;;;187    	rINTMSK &= ~(BIT_IIC);
000550  e51f004c          LDR      r0,|L1.1292|
000554  e5900008          LDR      r0,[r0,#8]
000558  e3c00680          BIC      r0,r0,#0x8000000
00055c  e51f1058          LDR      r1,|L1.1292|
000560  e5810008          STR      r0,[r1,#8]
;;;188    
;;;189    	//Enable ACK, Prescaler IICCLK=PCLK/512, Enable interrupt, Transmit clock value Tx clock=IICCLK/16
;;;190    	rIICCON  = (1<<7) | (1<<6) | (1<<5) | (0xf);
000564  e3a000ef          MOV      r0,#0xef
000568  e2811644          ADD      r1,r1,#0x4400000
00056c  e5810000          STR      r0,[r1,#0]
;;;191    
;;;192    	rIICADD  = 0x10;                    //24A0 slave address = [7:1]
000570  e3a00010          MOV      r0,#0x10

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