plx9080.h

rtlinux-3.2-pre3.tar.bz2 rtlinux3.2-pre3的源代码

#define PLX_DMA0_TRANSFER_SIZE_REG	0x8c	// number of bytes to transfer (first 23 bits)
#define PLX_DMA1_TRANSFER_SIZE_REG	0xa0

#define PLX_DMA0_DESCRIPTOR_REG	0x90	// descriptor pointer register
#define PLX_DMA1_DESCRIPTOR_REG	0xa4
#define  PLX_DESC_IN_PCI_BIT	0x1	// descriptor is located in pci space (not local space)
#define  PLX_END_OF_CHAIN_BIT	0x2	// end of chain bit
#define  PLX_INTR_TERM_COUNT	0x4	// interrupt when this descriptor's transfer is finished
#define  PLX_XFER_LOCAL_TO_PCI 0x8	// transfer from local to pci bus (not pci to local)

#define PLX_DMA0_CS_REG	0xa8	// command status register
#define PLX_DMA1_CS_REG	0xa9
#define  PLX_DMA_EN_BIT	0x1	// enable dma channel
#define  PLX_DMA_START_BIT	0x2	// start dma transfer
#define  PLX_DMA_ABORT_BIT	0x4	// abort dma transfer
#define  PLX_CLEAR_DMA_INTR_BIT	0x8	// clear dma interrupt
#define  PLX_DMA_DONE_BIT	0x10	// transfer done status bit

#define PLX_DMA0_THRESHOLD_REG	0xb0	// command status register

/*
 * Accesses near the end of memory can cause the PLX chip
 * to pre-fetch data off of end-of-ram.  Limit the size of
 * memory so host-side accesses cannot occur.
 */

#define PLX_PREFETCH   32

/*
 * The PCI Interface, via the PCI-9060 Chip, has up to eight (8) Mailbox
 * Registers.  The PUTS (Power-Up Test Suite) handles the board-side
 * interface/interaction using the first 4 registers.  Specifications for
 * the use of the full PUTS' command and status interface is contained
 * within a separate SBE PUTS Manual.  The Host-Side Device Driver only
 * uses a subset of the full PUTS interface.
 */


/*****************************************/
/***    MAILBOX #(-1) - MEM ACCESS STS ***/
/*****************************************/

#define MBX_STS_VALID      0x57584744 /* 'WXGD' */
#define MBX_STS_DILAV      0x44475857 /* swapped = 'DGXW' */

/*****************************************/
/***    MAILBOX #0  -  PUTS STATUS     ***/
/*****************************************/

#define MBX_STS_MASK       0x000000ff /* PUTS Status Register bits */
#define MBX_STS_TMASK      0x0000000f /* register bits for TEST number */

#define MBX_STS_PCIRESET   0x00000100 /* Host issued PCI reset request */
#define MBX_STS_BUSY       0x00000080 /* PUTS is in progress */
#define MBX_STS_ERROR      0x00000040 /* PUTS has failed */
#define MBX_STS_RESERVED   0x000000c0 /* Undefined -> status in transition.
					 We are in process of changing
					 bits; we SET Error bit before
                                         RESET of Busy bit */

#define MBX_RESERVED_5     0x00000020 /* FYI: reserved/unused bit */
#define MBX_RESERVED_4     0x00000010 /* FYI: reserved/unused bit */


/******************************************/
/***    MAILBOX #1  -  PUTS COMMANDS    ***/
/******************************************/

/*
 * Any attempt to execute an unimplement command results in the PUTS
 * interface executing a NOOP and continuing as if the offending command
 * completed normally.  Note: this supplies a simple method to interrogate
 * mailbox command processing functionality.
 */

#define MBX_CMD_MASK       0xffff0000 /* PUTS Command Register bits */

#define MBX_CMD_ABORTJ     0x85000000 /* abort and jump */
#define MBX_CMD_RESETP     0x86000000 /* reset and pause at start */
#define MBX_CMD_PAUSE      0x87000000 /* pause immediately */
#define MBX_CMD_PAUSEC     0x88000000 /* pause on completion */
#define MBX_CMD_RESUME     0x89000000 /* resume operation */
#define MBX_CMD_STEP       0x8a000000 /* single step tests */

#define MBX_CMD_BSWAP      0x8c000000 /* identify byte swap scheme */
#define MBX_CMD_BSWAP_0    0x8c000000 /* use scheme 0 */
#define MBX_CMD_BSWAP_1    0x8c000001 /* use scheme 1 */

#define MBX_CMD_SETHMS     0x8d000000 /* setup host memory access window
					 size */
#define MBX_CMD_SETHBA     0x8e000000 /* setup host memory access base
					 address */
#define MBX_CMD_MGO        0x8f000000 /* perform memory setup and continue
					 (IE. Done) */
#define MBX_CMD_NOOP       0xFF000000 /* dummy, illegal command */

/*****************************************/
/***    MAILBOX #2  -  MEMORY SIZE     ***/
/*****************************************/

#define MBX_MEMSZ_MASK     0xffff0000 /* PUTS Memory Size Register bits */

#define MBX_MEMSZ_128KB    0x00020000 /* 128 kilobyte board */
#define MBX_MEMSZ_256KB    0x00040000 /* 256 kilobyte board */
#define MBX_MEMSZ_512KB    0x00080000 /* 512 kilobyte board */
#define MBX_MEMSZ_1MB      0x00100000 /* 1 megabyte board */
#define MBX_MEMSZ_2MB      0x00200000 /* 2 megabyte board */
#define MBX_MEMSZ_4MB      0x00400000 /* 4 megabyte board */
#define MBX_MEMSZ_8MB      0x00800000 /* 8 megabyte board */
#define MBX_MEMSZ_16MB     0x01000000 /* 16 megabyte board */


/***************************************/
/***    MAILBOX #2  -  BOARD TYPE    ***/
/***************************************/

#define MBX_BTYPE_MASK          0x0000ffff /* PUTS Board Type Register */
#define MBX_BTYPE_FAMILY_MASK   0x0000ff00 /* PUTS Board Family Register */
#define MBX_BTYPE_SUBTYPE_MASK  0x000000ff /* PUTS Board Subtype */

#define MBX_BTYPE_PLX9060       0x00000100 /* PLX family type */
#define MBX_BTYPE_PLX9080       0x00000300 /* PLX wanXL100s family type */

#define MBX_BTYPE_WANXL_4       0x00000104 /* wanXL400, 4-port */
#define MBX_BTYPE_WANXL_2       0x00000102 /* wanXL200, 2-port */
#define MBX_BTYPE_WANXL_1s      0x00000301 /* wanXL100s, 1-port */
#define MBX_BTYPE_WANXL_1t      0x00000401 /* wanXL100T1, 1-port */


/*****************************************/
/***    MAILBOX #3  -  SHMQ MAILBOX    ***/
/*****************************************/

#define MBX_SMBX_MASK           0x000000ff /* PUTS SHMQ Mailbox bits */


/***************************************/
/***    GENERIC HOST-SIDE DRIVER     ***/
/***************************************/

#define MBX_ERR    0
#define MBX_OK     1

/* mailbox check routine - type of testing */
#define MBXCHK_STS      0x00    /* check for PUTS status */
#define MBXCHK_NOWAIT   0x01    /* dont care about PUTS status */

/* system allocates this many bytes for address mapping mailbox space */
#define MBX_ADDR_SPACE_360 0x80	/* wanXL100s/200/400 */
#define MBX_ADDR_MASK_360 (MBX_ADDR_SPACE_360-1)

static inline int plx9080_abort_dma( unsigned long iobase, unsigned int channel )
{
	unsigned long dma_cs_addr;
	uint8_t dma_status;
	const int timeout = 10000;
	unsigned int i;

	if( channel )
		dma_cs_addr = iobase + PLX_DMA1_CS_REG;
	else
		dma_cs_addr = iobase + PLX_DMA0_CS_REG;

	// abort dma transfer if necessary
	dma_status = readb( dma_cs_addr );
	if( ( dma_status & PLX_DMA_EN_BIT ) == 0 )
	{
		return 0;
	}

	// wait to make sure done bit is zero
	for( i = 0; ( dma_status & PLX_DMA_DONE_BIT ) && i < timeout; i++ )
	{
		dma_status = readb( dma_cs_addr );
		comedi_udelay( 1 );
	}
	if( i == timeout )
	{
		rt_printk("plx9080: cancel() timed out waiting for dma %i done clear\n", channel);
		return -ETIMEDOUT;
	}
	// disable channel
	writeb( 0, dma_cs_addr );
	comedi_udelay( 1 );
	// abort channel
	writeb( PLX_DMA_ABORT_BIT, dma_cs_addr );
	// wait for dma done bit
	dma_status = readb( dma_cs_addr );
	for( i = 0; ( dma_status & PLX_DMA_DONE_BIT ) == 0 && i < timeout; i++ )
	{
		comedi_udelay( 1 );
		dma_status = readb( dma_cs_addr );
	}
	if( i == timeout )
	{
		rt_printk("plx9080: cancel() timed out waiting for dma %i done set\n", channel);
		return -ETIMEDOUT;
	}

	return 0;
}

#endif /* __COMEDI_PLX9080_H */