adv_pci_dio.c

rtlinux-3.2-pre3.tar.bz2 rtlinux3.2-pre3的源代码

/*
 * comedi/drivers/adv_pci_dio.c
 *
 * Author: Michal Dobes <[e-mail]>
 *
 *  Hardware driver for Advantech PCI DIO cards.
*/
/*
Driver: adv_pci_dio.o
Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1750, PCI-1751,
             Advantech PCI-1752, PCI-1753/E, PCI-1754, PCI-1756, PCI-1762
Author: Michal Dobes <[e-mail]>
Devices: [Advantech] PCI-1730 (pci1730), PCI-1733 (pci1733),
  PCI-1734 (pci1734), PCI-1750 (pci1750), PCI-1751 (pci1751),
  PCI-1752 (pci1752), PCI-1753 (pci1753), PCI-1753+PCI-1753E (pci1753e),
  PCI-1754 (pci1754), PCI-1756 (pci1756), PCI-1760(pci1760), 
  PCI-1762 (pci1762)
Status: untested
Updated: 2003-04-06

This driver supports now only insn interface for DI/DO/DIO.

Configuration options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
          If bus/slot is not specified, the first available PCI
          device will be used.

*/

#include <linux/comedidev.h>

#include <linux/pci.h>
#include <linux/delay.h>

#include "8255.h"

#undef PCI_DIO_EXTDEBUG	/* if defined, enable extensive debug logging */

#undef DPRINTK
#ifdef PCI_DIO_EXTDEBUG
#define DPRINTK(fmt, args...) rt_printk(fmt, ## args)
#else
#define DPRINTK(fmt, args...)
#endif

// hardware types of the cards
typedef enum {
	TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734,
	TYPE_PCI1750, 
	TYPE_PCI1751,
	TYPE_PCI1752, 
	TYPE_PCI1753, TYPE_PCI1753E,
	TYPE_PCI1754, TYPE_PCI1756,
	TYPE_PCI1760,
	TYPE_PCI1762
} hw_cards_id;

// which I/O instructions to use
typedef enum {
	IO_8b, IO_16b
} hw_io_access;

#define MAX_DI_SUBDEVS	2	/* max number of DI subdevices per card */
#define MAX_DO_SUBDEVS	2	/* max number of DO subdevices per card */
#define MAX_DIO_SUBDEVG	2	/* max number of DIO subdevices group per card */

#define SIZE_8255	   4	/* 8255 IO space length */

#define PCIDIO_MAINREG	   2		/* main I/O region for all Advantech cards? */

/* Register offset definitions */
// Advantech PCI-1730/3/4
#define PCI1730_IDI	   0		/* R:   Isolated digital input  0-15 */
#define PCI1730_IDO	   0		/* W:   Isolated digital output 0-15 */
#define PCI1730_DI	   2		/* R:   Digital input  0-15 */
#define PCI1730_DO	   2		/* W:   Digital output 0-15 */
#define PCI1733_IDI	   0		/* R:   Isolated digital input  0-31 */
#define	PCI1730_3_INT_EN	0x08	/* R/W: enable/disable interrupts */
#define	PCI1730_3_INT_RF	0x0c	/* R/W: set falling/raising edge for interrupts */
#define	PCI1730_3_INT_CLR	0x10	/* R/W: clear interrupts */
#define PCI1734_IDO	   0		/* W:   Isolated digital output 0-31 */
#define PCI173x_BOARDID	   4		/* R:   Board I/D switch for 1730/3/4 */

// Advantech PCI-1750
#define PCI1750_IDI	   0		/* R:   Isolated digital input  0-15 */
#define PCI1750_IDO	   0		/* W:   Isolated digital output 0-15 */
#define PCI1750_ICR	  32		/* W:   Interrupt control register */
#define PCI1750_ISR	  32		/* R:   Interrupt status register */

// Advantech PCI-1751/3/3E
#define PCI1751_DIO	   0		/* R/W: begin of 8255 registers block */
#define PCI1751_ICR	  32		/* W:   Interrupt control register */
#define PCI1751_ISR	  32		/* R:   Interrupt status register */
#define PCI1753_DIO	   0		/* R/W: begin of 8255 registers block */
#define PCI1753_ICR0	  17		/* R/W: Interrupt control register group 0 */
#define PCI1753_ICR1	  18		/* R/W: Interrupt control register group 0 */
#define PCI1753_ICR2	  19		/* R/W: Interrupt control register group 0 */
#define PCI1753_ICR3	  48		/* R/W: Interrupt control register group 0 */
#define PCI1753E_DIO	  32		/* R/W: begin of 8255 registers block */
#define PCI1753E_ICR0	  49		/* R/W: Interrupt control register group 0 */
#define PCI1753E_ICR1	  50		/* R/W: Interrupt control register group 0 */
#define PCI1753E_ICR2	  51		/* R/W: Interrupt control register group 0 */
#define PCI1753E_ICR3	  52		/* R/W: Interrupt control register group 0 */


// Advantech PCI-1752/4/6
#define PCI1752_IDO	   0		/* R/W: Digital output  0-31 */
#define PCI1752_IDO2	   4		/* R/W: Digital output 32-63 */
#define PCI1754_IDI	   0		/* R:   Digital input   0-31 */
#define PCI1754_IDI2	   4		/* R:   Digital input  32-64 */
#define PCI1756_IDI	   0		/* R:   Digital input   0-31 */
#define PCI1756_IDO	   4		/* R/W: Digital output  0-31 */
#define PCI1754_6_ICR0	0x08		/* R/W: Interrupt control register group 0 */
#define PCI1754_6_ICR1	0x0a		/* R/W: Interrupt control register group 1 */
#define PCI1754_ICR2	0x0c		/* R/W: Interrupt control register group 2 */
#define PCI1754_ICR3	0x0e		/* R/W: Interrupt control register group 3 */
#define PCI1752_6_CFC	0x12		/* R/W: set/read channel freeze function */
#define PCI175x_BOARDID	0x10		/* R:   Board I/D switch for 1752/4/6 */

// Advantech PCI-1762 registers
#define PCI1762_RO	   0		/* R/W: Relays status/output */
#define PCI1762_IDI	   0		/* R:   Isolated input status */
#define PCI1762_BOARDID	   4		/* R:   Board I/D switch */
#define PCI1762_ICR	   6		/* W:   Interrupt control register */
#define PCI1762_ISR	   6		/* R:   Interrupt status register */

// Advantech PCI-1760 registers
#define OMB0		0x0c		/* W:   Mailbox outgoing registers */
#define OMB1		0x0d
#define OMB2		0x0e
#define OMB3		0x0f
#define IMB0		0x1c		/* R:   Mailbox incoming registers */
#define IMB1		0x1d
#define IMB2		0x1e
#define IMB3		0x1f
#define INTCSR0		0x38		/* R/W: Interrupt control registers */
#define INTCSR1		0x39
#define INTCSR2		0x3a
#define INTCSR3		0x3b

// PCI-1760 mailbox commands
#define CMD_ClearIMB2		0x00	/* Clear IMB2 status and return actaul DI status in IMB3 */
#define CMD_SetRelaysOutput	0x01	/* Set relay output from OMB0 */
#define CMD_GetRelaysStatus	0x02	/* Get relay status to IMB0 */
#define CMD_ReadCurrentStatus	0x07	/* Read the current status of the register in OMB0, result in IMB0 */
#define CMD_ReadFirmwareVersion	0x0e	/* Read the firmware ver., result in IMB1.IMB0 */
#define CMD_ReadHardwareVersion	0x0f	/* Read the hardware ver., result in IMB1.IMB0 */
#define CMD_EnableIDIFilters	0x20	/* Enable IDI filters based on bits in OMB0 */
#define CMD_EnableIDIPatternMatch 0x21	/* Enable IDI pattern match based on bits in OMB0 */
#define CMD_SetIDIPatternMatch	0x22	/* Enable IDI pattern match based on bits in OMB0 */
#define CMD_EnableIDICounters	0x28	/* Enable IDI counters based on bits in OMB0 */
#define CMD_ResetIDICounters	0x29	/* Reset IDI counters based on bits in OMB0 to its reset values */
#define CMD_OverflowIDICounters	0x2a	/* Enable IDI counters overflow interrupts  based on bits in OMB0 */
#define CMD_MatchIntIDICounters	0x2b	/* Enable IDI counters match value interrupts  based on bits in OMB0 */
#define CMD_EdgeIDICounters	0x2c	/* Set IDI up counters count edge (bit=0 - rising, =1 - falling) */
#define CMD_GetIDICntCurValue	0x2f	/* Read IDI{OMB0} up counter current value */
#define CMD_SetIDI0CntResetValue 0x40	/* Set IDI0 Counter Reset Value 256*OMB1+OMB0 */
#define CMD_SetIDI1CntResetValue 0x41	/* Set IDI1 Counter Reset Value 256*OMB1+OMB0 */
#define CMD_SetIDI2CntResetValue 0x42	/* Set IDI2 Counter Reset Value 256*OMB1+OMB0 */
#define CMD_SetIDI3CntResetValue 0x43	/* Set IDI3 Counter Reset Value 256*OMB1+OMB0 */
#define CMD_SetIDI4CntResetValue 0x44	/* Set IDI4 Counter Reset Value 256*OMB1+OMB0 */
#define CMD_SetIDI5CntResetValue 0x45	/* Set IDI5 Counter Reset Value 256*OMB1+OMB0 */
#define CMD_SetIDI6CntResetValue 0x46	/* Set IDI6 Counter Reset Value 256*OMB1+OMB0 */
#define CMD_SetIDI7CntResetValue 0x47	/* Set IDI7 Counter Reset Value 256*OMB1+OMB0 */
#define CMD_SetIDI0CntMatchValue 0x48	/* Set IDI0 Counter Match Value 256*OMB1+OMB0 */
#define CMD_SetIDI1CntMatchValue 0x49	/* Set IDI1 Counter Match Value 256*OMB1+OMB0 */
#define CMD_SetIDI2CntMatchValue 0x4a	/* Set IDI2 Counter Match Value 256*OMB1+OMB0 */
#define CMD_SetIDI3CntMatchValue 0x4b	/* Set IDI3 Counter Match Value 256*OMB1+OMB0 */
#define CMD_SetIDI4CntMatchValue 0x4c	/* Set IDI4 Counter Match Value 256*OMB1+OMB0 */
#define CMD_SetIDI5CntMatchValue 0x4d	/* Set IDI5 Counter Match Value 256*OMB1+OMB0 */
#define CMD_SetIDI6CntMatchValue 0x4e	/* Set IDI6 Counter Match Value 256*OMB1+OMB0 */
#define CMD_SetIDI7CntMatchValue 0x4f	/* Set IDI7 Counter Match Value 256*OMB1+OMB0 */

#define OMBCMD_RETRY	0x03		/* 3 times try request before error */

static int pci_dio_attach(comedi_device *dev,comedi_devconfig *it);
static int pci_dio_detach(comedi_device *dev);

typedef struct {
	int		chans;		// num of chans
	int		addr;		// PCI address ofset
	int		regs;		// number of registers to read or 8255 subdevices
	unsigned int	specflags;	// addon subdevice flags
} diosubd_data;

typedef struct {
	char 		*name;		// driver name
	int		vendor_id;	// vendor/device PCI ID
	int		device_id;
	int		main_pci_region;// main I/O OCI region
	hw_cards_id	cardtype;	// {enum hw_cards_id_enum}
	diosubd_data 	sdi[MAX_DI_SUBDEVS];	// DI chans
	diosubd_data	sdo[MAX_DO_SUBDEVS];	// DO chans
	diosubd_data	sdio[MAX_DIO_SUBDEVG];	// DIO 8255 chans
	diosubd_data	boardid;	// card supports board ID switch
	hw_io_access	io_access;	// {enum hw_io_access_enum}
} boardtype;

static struct pci_device_id pci_dio_pci_table[] = __devinitdata {
	{ PCI_VENDOR_ID_ADVANTECH, 0x1730, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ADVANTECH, 0x1733, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ADVANTECH, 0x1734, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ADVANTECH, 0x1750, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ADVANTECH, 0x1751, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ADVANTECH, 0x1752, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ADVANTECH, 0x1753, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ADVANTECH, 0x1754, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ADVANTECH, 0x1756, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ADVANTECH, 0x1760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ADVANTECH, 0x1762, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, pci_dio_pci_table);

static boardtype boardtypes[] =
{
	{"pci1730", PCI_VENDOR_ID_ADVANTECH, 0x1730, PCIDIO_MAINREG,
	 TYPE_PCI1730,
	 {{16, PCI1730_DI, 2, 0}, {16, PCI1730_IDI, 2, 0}},
	 {{16, PCI1730_DO, 2, 0}, {16, PCI1730_IDO, 2, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	  { 4, PCI173x_BOARDID, 1, SDF_INTERNAL},
	 IO_8b, 
	},
	{"pci1733", PCI_VENDOR_ID_ADVANTECH, 0x1733, PCIDIO_MAINREG,
	 TYPE_PCI1733,
	 {{ 0, 0, 0, 0}, {32, PCI1733_IDI, 4, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	  { 4, PCI173x_BOARDID, 1, SDF_INTERNAL},
	 IO_8b
	},
	{"pci1734", PCI_VENDOR_ID_ADVANTECH, 0x1734, PCIDIO_MAINREG,
	 TYPE_PCI1734,
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{ 0, 0, 0, 0}, {32, PCI1734_IDO, 4,  0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	  { 4, PCI173x_BOARDID, 1, SDF_INTERNAL},
	 IO_8b
	},
	{"pci1750", PCI_VENDOR_ID_ADVANTECH, 0x1750, PCIDIO_MAINREG,
	 TYPE_PCI1750,
	 {{ 0, 0, 0, 0}, {16, PCI1750_IDI, 2, 0}},
	 {{ 0, 0, 0, 0}, {16, PCI1750_IDO, 2, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	  { 0, 0, 0, 0},
	 IO_8b
	},
	{"pci1751", PCI_VENDOR_ID_ADVANTECH, 0x1751, PCIDIO_MAINREG,
	 TYPE_PCI1751,
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{48, PCI1751_DIO, 2, 0}, { 0, 0, 0, 0}},
	  { 0, 0, 0, 0},
	 IO_8b
	},
	{"pci1752", PCI_VENDOR_ID_ADVANTECH, 0x1752, PCIDIO_MAINREG,
	 TYPE_PCI1752,
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{32, PCI1752_IDO, 2, 0}, {32, PCI1752_IDO2, 2, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	  { 4, PCI175x_BOARDID, 1, SDF_INTERNAL},
	 IO_16b
	},
	{"pci1753", PCI_VENDOR_ID_ADVANTECH, 0x1753, PCIDIO_MAINREG,
	 TYPE_PCI1753,
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{96, PCI1753_DIO, 4, 0}, { 0, 0, 0, 0}},
	  { 0, 0, 0, 0},
	 IO_8b
	},
	{"pci1753e", PCI_VENDOR_ID_ADVANTECH, 0x1753, PCIDIO_MAINREG,
	 TYPE_PCI1753E,
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{96, PCI1753_DIO, 4, 0}, {96, PCI1753E_DIO, 4, 0}},
	  { 0, 0, 0, 0},
	 IO_8b
	},
	{"pci1754", PCI_VENDOR_ID_ADVANTECH, 0x1754, PCIDIO_MAINREG,
	 TYPE_PCI1754,
	 {{32, PCI1754_IDI, 2, 0}, {32, PCI1754_IDI2, 2, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	  { 4, PCI175x_BOARDID, 1, SDF_INTERNAL},
	 IO_16b
	},
	{"pci1756", PCI_VENDOR_ID_ADVANTECH, 0x1756, PCIDIO_MAINREG,
	 TYPE_PCI1756,
	 {{ 0, 0, 0, 0}, {32, PCI1756_IDI, 2, 0}},
	 {{ 0, 0, 0, 0}, {32, PCI1756_IDO, 2, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	  { 4, PCI175x_BOARDID, 1, SDF_INTERNAL},
	 IO_16b
	},
	{"pci1760", PCI_VENDOR_ID_ADVANTECH, 0x1760, PCIDIO_MAINREG,
	 TYPE_PCI1760,
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},	// This card have own setup work
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	  { 0, 0, 0, 0},
	 IO_8b
	},
	{"pci1762", PCI_VENDOR_ID_ADVANTECH, 0x1762, PCIDIO_MAINREG,
	 TYPE_PCI1762,
	 {{ 0, 0, 0, 0}, {16, PCI1762_IDI, 1, 0}},
	 {{ 0, 0, 0, 0}, {16, PCI1762_RO, 1, 0}},
	 {{ 0, 0, 0, 0}, { 0, 0, 0, 0}},
	  { 4, PCI1762_BOARDID, 1, SDF_INTERNAL},
	 IO_16b
	}
};

#define n_boardtypes (sizeof(boardtypes)/sizeof(boardtype))

static comedi_driver driver_pci_dio={
	driver_name:	"adv_pci_dio",
	module:		THIS_MODULE,
	attach:		pci_dio_attach,
	detach:		pci_dio_detach,
	num_names:	n_boardtypes,
	board_name:	boardtypes,
	offset:		sizeof(boardtype),
};
typedef struct pci_dio_private_st pci_dio_private;
struct pci_dio_private_st {
	pci_dio_private		*prev;		// previous private struct
	pci_dio_private		*next;		// next private struct
	struct pci_dev 		*pcidev;	// pointer to board's pci_dev
	char			valid;		// card is usable
	char			enabled;	// PCI card is enabled
	char			GlobalIrqEnabled;// 1= any IRQ source is enabled
	// PCI-1760 specific data
	unsigned char		IDICntEnable;	// counter's counting enable status
	unsigned char		IDICntOverEnable;// counter's overflow interrupts enable status
	unsigned char		IDICntMatchEnable;// counter's match interrupts enable status
	unsigned char		IDICntEdge;	// counter's count edge value (bit=0 - rising, =1 - falling)
	unsigned short		CntResValue[8];	// counters' reset value
	unsigned short		CntMatchValue[8];// counters' match interrupt value
	unsigned char		IDIFiltersEn;	// IDI's digital filters enable status
	unsigned char		IDIPatMatchEn;	// IDI's pattern match enable status
	unsigned char		IDIPatMatchValue;// IDI's pattern match value
	unsigned short		IDIFiltrLow[8];	// IDI's filter value low signal
	unsigned short		IDIFiltrHigh[8];// IDI's filter value high signal
};

static pci_dio_private	*pci_priv=NULL;	/* list of allocated cards */