rom_512x16a_typical_syn.lib

TSMC 130NM的DESIGN LIBRARY。

/*
 *      CONFIDENTIAL AND PROPRIETARY SOFTWARE/DATA OF ARTISAN COMPONENTS, INC.
 *      
 *      Copyright (c) 2003 Artisan Components, Inc.  All Rights Reserved.
 *      
 *      Use of this Software/Data is subject to the terms and conditions of
 *      the applicable license agreement between Artisan Components, Inc. and
 *      Taiwan Semiconductor Manufacturing Company Ltd..  In addition, this Software/Data
 *      is protected by copyright law and international treaties.
 *      
 *      The copyright notice(s) in this Software/Data does not indicate actual
 *      or intended publication of this Software/Data.
 *      name:			ROM-DIFF-HS ROM Generator
 *           			TSMC CL013G Process
 *      version:		2002Q3V1
 *      comment:		
 *      configuration:	 -instname "rom_512x16A" -words 512 -bits 16 -frequency 166 -ring_width 8 -code_file "/net/abilene/usr2/soce3.2_workshop/lab_data_3.2/SOCE-3.2_workshop/library.tsmc18/verilog/rom_512x16A_verilog.rcf" -mux 8 -drive 6 -top_layer met8 -power_type rings -horiz met3 -vert met4 -cust_comment "" -left_bus_delim "[" -right_bus_delim "]" -pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper -check_instname on -diodes on -inside_ring_type GND -libname USERLIB
 *
 *      Synopsys model for Synchronous Single-Port Rom
 *
 *      Library Name:   USERLIB
 *      Instance Name:  rom_512x16A
 *      Words:          512
 *      Word Width:     16
 *      Mux:            8
 *      Process:        typical
 *      Delays:		max
 *
 *      Creation Date:  2003-10-28 01:00:31Z
 *      Version:        2002Q3V1
 *
 *      Verified With: Synopsys Design Compiler
 *
 *      Modeling Assumptions: This library contains a black box description
 *          for a memory element.  At the library level, a
 *          default_max_transition constraint is set to the maximum
 *          characterized input slew.  Each output has a max_capacitance
 *          constraint set to the highest characterized output load.  These two
 *          constraints force Design Compiler to synthesize circuits that
 *          operate within the characterization space.  The user can tighten
 *          these constraints, if desired.  When writing SDF from Design
 *          Compiler, use the version 2.1 option.  This ensures the SDF will
 *          annotate to simulation models provided with this generator.
 *
 *      Modeling Limitations: This library does not include power information.
 *          Due to limitations of the .lib format, some data reduction was
 *          necessary.  When reducing data, minimum values were chosen for the
 *          fast case corner and maximum values were used for the typical and
 *          best case corners.  It is recommended that critical timing and
 *          setup and hold times be checked at all corners.
 *
 *      Known Bugs: None.
 *
 *      Known Work Arounds: N/A
 *
 */

library(USERLIB) {
	delay_model		: table_lookup;
	revision		: 1.1;	
	date			: "2003-10-28 01:00:31Z";
	comment			: "Confidential Information of Artisan Components, Inc.  Use subject to Artisan Components license. Copyright (c) 2003 Artisan Components, Inc.";
	time_unit		: "1ns";
	voltage_unit		: "1V";
	current_unit		: "1mA";
	leakage_power_unit	: "1mW";
	nom_process		: 1;
	nom_temperature		: 25.000;
	nom_voltage		: 1.200;
	capacitive_load_unit	 (1,pf);

	pulling_resistance_unit	        : "1kohm";

	/* additional header data */
	default_cell_leakage_power      : 0;
	default_fanout_load		: 1;
	default_inout_pin_cap		: 0.005;
	default_input_pin_cap		: 0.005;
	default_output_pin_cap		: 0.0;
	default_max_transition		: 1.000;

        /* default attributes */
        default_leakage_power_density : 0.0;
        slew_derate_from_library      : 1;
        slew_lower_threshold_pct_fall : 10.0;
        slew_upper_threshold_pct_fall : 90.0;
        slew_lower_threshold_pct_rise : 10.0;
        slew_upper_threshold_pct_rise : 90.0;
        input_threshold_pct_fall      : 50.0;
        input_threshold_pct_rise      : 50.0;
        output_threshold_pct_fall     : 50.0;
        output_threshold_pct_rise     : 50.0;

 	/* k-factors */
 	k_process_cell_fall             : 1;
 	k_process_cell_leakage_power    : 0;
 	k_process_cell_rise             : 1;
 	k_process_fall_transition       : 1;
 	k_process_hold_fall             : 1;
 	k_process_hold_rise             : 1;
 	k_process_internal_power        : 0;
 	k_process_min_pulse_width_high  : 1;
 	k_process_min_pulse_width_low   : 1;
 	k_process_pin_cap               : 0;
 	k_process_recovery_fall         : 1;
 	k_process_recovery_rise         : 1;
 	k_process_rise_transition       : 1;
 	k_process_setup_fall            : 1;
 	k_process_setup_rise            : 1;
 	k_process_wire_cap              : 0;
 	k_process_wire_res              : 0;
	k_temp_cell_fall		: 0.0;
	k_temp_cell_rise		: 0.0;
	k_temp_hold_fall                : 0.0;
	k_temp_hold_rise                : 0.0;
	k_temp_min_pulse_width_high     : 0.0;
	k_temp_min_pulse_width_low      : 0.0;
	k_temp_min_period               : 0.0;
	k_temp_rise_propagation         : 0.0;
	k_temp_fall_propagation         : 0.0;
	k_temp_rise_transition          : 0.0;
	k_temp_fall_transition          : 0.0;
	k_temp_recovery_fall            : 0.0;
	k_temp_recovery_rise            : 0.0;
	k_temp_setup_fall               : 0.0;
	k_temp_setup_rise               : 0.0;
	k_volt_cell_fall                : 0.0;
	k_volt_cell_rise                : 0.0;
	k_volt_hold_fall                : 0.0;
	k_volt_hold_rise                : 0.0;
	k_volt_min_pulse_width_high     : 0.0;
	k_volt_min_pulse_width_low      : 0.0;
	k_volt_min_period               : 0.0;
	k_volt_rise_propagation         : 0.0;
	k_volt_fall_propagation         : 0.0;
	k_volt_rise_transition	        : 0.0;
	k_volt_fall_transition	        : 0.0;
	k_volt_recovery_fall            : 0.0;
	k_volt_recovery_rise            : 0.0;
	k_volt_setup_fall               : 0.0;
	k_volt_setup_rise               : 0.0;


	operating_conditions(typical) {
		process	 : 1;
		temperature	 : 25.000;
		voltage	 : 1.200;
		tree_type	 : balanced_tree;
	}
        default_operating_conditions : typical;
	wire_load("sample") {
		resistance	 : 1.6e-05;
		capacitance	 : 0.0002;
		area	 : 1.7;
  		slope	 : 500;
		fanout_length	 (1,500);
	}
	output_voltage(GENERAL) {
		vol	 : 0.4;
		voh	 : VDD - 0.4;
		vomin	 : -0.5;
		vomax	 : VDD + 0.5;
	}
	input_voltage(CMOS) {
		vil	 : 0.3 * VDD;
		vih	 : 0.7 * VDD;
		vimin	 : -0.5;
		vimax	 : VDD + 0.5;
	}
	input_voltage(TTL) {
		vil	 : 0.8;
		vih	 : 2;
		vimin	 : -0.5;
		vimax	 : VDD + 0.5;
	}
        lu_table_template(rom_512x16A_delay_template) {
           variable_1 : input_net_transition;
           variable_2 : total_output_net_capacitance;
               index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
               index_2 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
        }
	lu_table_template(rom_512x16A_constraint_template) {
           variable_1 : related_pin_transition;
           variable_2 : constrained_pin_transition;
               index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
               index_2 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
        }
	lu_table_template(rom_512x16A_load_template) {
           variable_1 : total_output_net_capacitance;
               index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
        }
        power_lut_template(rom_512x16A_passive_energy_template_1x2) {
           variable_1 : input_transition_time;
               index_1 ("1000, 1001");
        }
	library_features(report_delay_calculation);
	type (rom_512x16A_DATA) {
		base_type : array ;
		data_type : bit ;
		bit_width : 16;
		bit_from : 15;
		bit_to : 0 ;
		downto : true ;
	}
	type (rom_512x16A_ADDRESS) {
		base_type : array ;
		data_type : bit ;
		bit_width : 9;
		bit_from : 8;
		bit_to : 0 ;
		downto : true ;
	}