register_test.v

来自「register,原程序及testbench,供初学者参考」· Verilog 代码 · 共 48 行

/**********************************************************************
 * Stimulus for testing the 8-bit Register - Verilog Training Course
 *********************************************************************/
`timescale 1 ns / 100 ps

module test;
  wire [7:0] reg_out;              //declare vector for register output
  reg  [7:0] data;
  reg        ena, rst;

  register r1(reg_out, clk, data, ena, rst);

  clock c1 (clk);      //clock oscilator

  initial              //display inputs & outputs as waveform
     begin
       $shm_open ("register.shm");
       $shm_probe("A");
       #100 $finish;
     end

/*********************************************************************
  SPECIFY INPUT STIMULI 
*********************************************************************/

  initial 
    begin
// initialize inputs
      rst = 1;  
      ena = 0;
      data = 8'h5f;     // Output should be unknown

// test that reset works
      #5 rst = 0; 
      ena = 1;         // Output should go to zero

// test that enable works
      #15 rst = 1;     // Output should be clocked from data
      #20 data = 8'h3d; 
      #20 ena = 0;
      data = 8'h19;     // Output should not be clocked from data.
    end

endmodule