register.v

来自「register,原程序及testbench,供初学者参考」· Verilog 代码 · 共 18 行

/*****************************************************************************
 * 8-bit register with hierarchy, Verilog Training Course
 ****************************************************************************/

`timescale 1 ns / 100 ps
module register(r, clk, data, ena, rst);
  output [7:0] r;
  input  [7:0] data;
  input        clk, ena, rst;

  wire   [7:0] r_in;

  mux1   m[7:0] (ena, r, data, r_in);

  dffr_b d[7:0] (rst, clk, r, , r_in);

endmodule