mux1.v

来自「register,原程序及testbench,供初学者参考」· Verilog 代码 · 共 22 行

`celldefine
module mux1(ena,a,b,y);
output y;
input a, b, ena;  // Select b if ena is high (logic 1)

  not (ena_not, ena);
  and (a_int, ena_not, a);
  and (b_int, ena, b);
  or  (y, a_int, b_int);

specify
// Path Delays
    (a,b,ena => y) = 1.1;

// Intrinsic characteristics that affect timing
    specparam cell_area=466.56,		// layout area
	max_load$ = 0.8,		// maximum load
	resistance$y=0.8, slope$y=0.2, capacitance$=0.044;
endspecify
endmodule
`endcelldefine