nand2_b.v

来自「register,原程序及testbench,供初学者参考」· Verilog 代码 · 共 20 行

`celldefine
module nand2_b(y,a,b);
input a,b;
output y;

nand (y, a, b);

specify
// Path Delays
    (a,b => y) = 0.64;

// Intrinsic characteristics that affect timing
    specparam cell_area=207.36,           // layout area
    	max_load$ = 0.8,		  // maximum load
    	resistance$y=1.2, slope$y=0.2, capacitance$=0.044;
endspecify
endmodule
`endcelldefine