nand3_b.v

来自「register,原程序及testbench,供初学者参考」· Verilog 代码 · 共 20 行

`celldefine
module nand3_b(y,a,b,c);
input a,b,c;
output y;

nand (y, a, b, c);

specify
// Path Delays
    (a,b,c => y) = 0.89;

// Intrinsic characteristics that affect timing
    specparam cell_area=259.2,           // layout area
	max_load$ = 0.5,		 // maximum load
	resistance$y=1.4, slope$y=0.2, capacitance$=0.044; 
endspecify
endmodule
`endcelldefine