ccm.c

嵌入式linux的bsp

    memctl->memc_mdr = 0xFFFDCC05;
    memctl->memc_mcr = 0x011C | UPMB;

    /* Initialize OR3 / BR3 for CAN Bus Controller */
    memctl->memc_or3 = CFG_OR3_CAN;
    memctl->memc_br3 = CFG_BR3_CAN;
}

static void can_driver_disable (void)
{
    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
    volatile memctl8xx_t *memctl = &immap->im_memctl;

    /* Reset OR3 / BR3 to disable  CAN Bus Controller */
    memctl->memc_br3 = 0;
    memctl->memc_or3 = 0;

    memctl->memc_mbmr = 0;
}


/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
    volatile memctl8xx_t *memctl = &immap->im_memctl;
    volatile long int	 *addr;
    ulong		  cnt, val;
    ulong		  save[32];	/* to make test non-destructive */
    unsigned char	  i = 0;

    memctl->memc_mamr = mamr_value;

    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
	addr = base + cnt;	/* pointer arith! */

	save[i++] = *addr;
	*addr = ~cnt;
    }

    /* write 0 to base address */
    addr = base;
    save[i] = *addr;
    *addr = 0;

    /* check at base address */
    if ((val = *addr) != 0) {
	*addr = save[i];
	return (0);
    }

    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
	addr = base + cnt;	/* pointer arith! */

	val = *addr;
	*addr = save[--i];

	if (val != (~cnt)) {
	    return (cnt * sizeof(long));
	}
    }
    return (maxsize);
}

/* ------------------------------------------------------------------------- */

#define	ETH_CFG_BITS	(CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2  | CFG_PB_ETH_CFG3 )

#define ETH_ALL_BITS	(ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)

void	reset_phy(void)
{
	immap_t *immr = (immap_t *)CFG_IMMR;
	ulong value;

	/* Configure all needed port pins for GPIO */
#if CFG_ETH_MDDIS_VALUE
	immr->im_ioport.iop_padat |=   CFG_PA_ETH_MDDIS;
#else
	immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS);	/* Set low */
#endif
	immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS);	/* GPIO */
	immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS);	/* active output */
	immr->im_ioport.iop_padir |=   CFG_PA_ETH_MDDIS;	/* output */

	immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS);	/* GPIO */
	immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS);	/* active output */

	value  = immr->im_cpm.cp_pbdat;

	/* Assert Powerdown and Reset signals */
	value |=  CFG_PB_ETH_POWERDOWN;
	value &= ~(CFG_PB_ETH_RESET);

	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
#if CFG_ETH_CFG1_VALUE
	value |=   CFG_PB_ETH_CFG1;
#else
	value &= ~(CFG_PB_ETH_CFG1);
#endif
#if CFG_ETH_CFG2_VALUE
	value |=   CFG_PB_ETH_CFG2;
#else
	value &= ~(CFG_PB_ETH_CFG2);
#endif
#if CFG_ETH_CFG3_VALUE
	value |=   CFG_PB_ETH_CFG3;
#else
	value &= ~(CFG_PB_ETH_CFG3);
#endif

	/* Drive output signals to initial state */
	immr->im_cpm.cp_pbdat  = value;
	immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
	udelay (10000);

	/* De-assert Ethernet Powerdown */
	immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
	udelay (10000);

	/* de-assert RESET signal of PHY */
	immr->im_cpm.cp_pbdat |=   CFG_PB_ETH_RESET;
	udelay (1000);
}

/*-----------------------------------------------------------------------
 * Board Special Commands: access functions for "PUMA" FPGA
 */

#define	PUMA_READ_MODE	0
#define PUMA_LOAD_MODE	1

#if (CONFIG_COMMANDS & CFG_CMD_BSP)

void do_puma (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
	ulong addr, len;

	switch (argc) {
	case 2:			/* PUMA reset */
		if (strncmp(argv[1], "stat", 4) == 0) {		/* Reset */
			puma_status ();
			return;
		}
		break;
	case 4:			/* PUMA load addr len */
		if (strcmp(argv[1],"load") != 0)
			break;

		addr = simple_strtoul(argv[2], NULL, 16);
		len  = simple_strtoul(argv[3], NULL, 16);

		printf ("PUMA load: addr %08lX len %ld (0x%lX):  ",
			addr, len, len);
		puma_load (addr, len);

		return;
	default:
		break;
	}
	printf ("Usage:\n%s\n", cmdtp->usage);
}

#endif	/* CFG_CMD_BSP */

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

static void puma_set_mode (int mode)
{
	volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	/* disable PUMA in memory controller */
	memctl->memc_br4 = 0;
	
	switch (mode) {
	case PUMA_READ_MODE:
		memctl->memc_or4 = PUMA_CONF_OR_READ;
		memctl->memc_br4 = PUMA_CONF_BR_READ;
		
		/* (re-) enable CAN drivers */
		can_driver_enable ();

		break;
	case PUMA_LOAD_MODE:

		/*
		 * We must disable the CAN drivers first because
		 * they use UPM B, too.
		 */
		can_driver_disable ();

		/*
		 * Configure UPMB for PUMA
		 */
		upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));

		memctl->memc_or4 = PUMA_CONF_OR_LOAD;
		memctl->memc_br4 = PUMA_CONF_BR_LOAD;
		break;
	}
}

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

#define	PUMA_INIT_TIMEOUT	1000	/* max. 1000 ms = 1 second */

static void puma_load (ulong addr, ulong len)
{
	volatile immap_t *immr = (immap_t *)CFG_IMMR;
	volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */
	uchar *data = (uchar *)addr;
	int i;

	/* align length */
	if (len & 1)
		++len;

	/* Reset FPGA */
	immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT);	/* make input */
	immr->im_ioport.iop_pcso  &= ~(CFG_PC_PUMA_INIT);
	immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);

	immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG);		/* GPIO */
	immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG);		/* active output */
	immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG);		/* Set low */
	immr->im_cpm.cp_pbdir |=   CFG_PB_PUMA_PROG;		/* output */
	udelay (100);

	immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG;		/* release reset */

	/* wait until INIT indicates completion of reset */
	for (i=0; i<PUMA_INIT_TIMEOUT; ++i) {
		udelay (1000);
		if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
			break;
	}
	if (i == PUMA_INIT_TIMEOUT) {
		printf ("*** PUMA init timeout ***\n");
		return;
	}

	puma_set_mode (PUMA_LOAD_MODE);

	while (len--) {
		*fpga_addr = *data++;
	}

	puma_set_mode (PUMA_READ_MODE);

	puma_status ();
}

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

static void puma_status (void)
{
	/* Check state */
	printf ("PUMA initialization is %scomplete\n",
		puma_init_done() ? "" : "NOT ");
}

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

static int puma_init_done (void)
{
	volatile immap_t *immr = (immap_t *)CFG_IMMR;

	/* make sure pin is GPIO input */
	immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
	immr->im_ioport.iop_pcso  &= ~(CFG_PC_PUMA_DONE);
	immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);

	return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
}

/* ------------------------------------------------------------------------- */

void misc_init_r (bd_t *dummy)
{
	ulong addr = 0;
	ulong len  = 0;
	char *s;

	printf ("PUMA:  ");
	if (puma_init_done()) {
		printf ("initialized\n");
		return;
	}

	if ((s = getenv("puma_addr")) != NULL)
		addr = simple_strtoul(s, NULL, 16);

	if ((s = getenv("puma_len")) != NULL)
		len = simple_strtoul(s, NULL, 16);
	
	if ((!addr) || (!len)) {
		printf ("net list undefined\n");
		return;
	}

	printf ("loading... ");

	puma_load (addr, len);
}

/* ------------------------------------------------------------------------- */