init.s

嵌入式linux的bsp

                                          // via STRAP reg to calc PLB speed.
                                          // SDRAM speed is the same as the PLB
				          // speed.
        rlwinm  r4,r5,4,0x3             // get FBK divide bits

..chk_66:
        cmpi    %cr0,0,r4,0x1
        bne     ..chk_100
	addis	r6,0,0x0085		// SDTR1 value for 66Mhz
	ori     r6,r6,0x4005
	addis	r7,0,0x03F8		// RTR value for 66Mhz
        b	..sdram_ok
..chk_100:
        cmpi    %cr0,0,r4,0x2
        bne     ..chk_133
        addis   r6,0,0x0086            // SDTR1 value for 100Mhz
        ori     r6,r6,0x400D
        addis   r7,0,0x05F0            // RTR value for 100Mhz
        b       ..sdram_ok
..chk_133:
        addis   r6,0,0x0107            // SDTR1 value for 133Mhz
        ori     r6,r6,0x4015
        addis   r7,0,0x07F0            // RTR value for 133Mhz

..sdram_ok:
        //-------------------------------------------------------------------
        // Set SDTR1
        //-------------------------------------------------------------------
        addi    r4,0,mem_sdtr1
        mtdcr   memcfga,r4
        mtdcr   memcfgd,r6

        //-------------------------------------------------------------------
        // Set RTR
        //-------------------------------------------------------------------
        addi    r4,0,mem_rtr
        mtdcr   memcfga,r4
        mtdcr   memcfgd,r7

        //-------------------------------------------------------------------
        // Delay to ensure 200usec have elapsed since reset. Assume worst
        // case that the core is running 200Mhz:
        //   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
        //-------------------------------------------------------------------
        addis   r3,0,0x0000
        ori     r3,r3,0xA000          // ensure 200usec have passed since reset
        mtctr   r3
..spinlp2:
        bdnz    ..spinlp2               // spin loop

        //-------------------------------------------------------------------
        // Set memory controller options reg, MCOPT1.
	// Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
	// read/prefetch.
        //-------------------------------------------------------------------
        addi    r4,0,mem_mcopt1
        mtdcr   memcfga,r4
        addis   r4,0,0x8080             // set DC_EN=1
        ori     r4,r4,0x0000
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Delay to ensure 10msec have elapsed since reset. This is
        // required for the MPC952 to stabalize. Assume worst
        // case that the core is running 200Mhz:
        //   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
        // This delay should occur before accessing SDRAM.
        //-------------------------------------------------------------------
        addis   r3,0,0x001E
        ori     r3,r3,0x8480          // ensure 10msec have passed since reset
        mtctr   r3
..spinlp3:
        bdnz    ..spinlp3                // spin loop

        //-------------------------------------------------------------------
        // Test if 64MByte is ok.
        //-------------------------------------------------------------------
        addis   r3,0,MAGIC0@h
       	ori	r3,r3,MAGIC0@l
        addis   r4,0,ADDR_ZERO@h
        ori     r4,r4,ADDR_ZERO@l
        stw     r3,0x00(r4)            // store magic at 0
        addis   r3,0,MAGIC1@h
       	ori	r3,r3,MAGIC1@l
        addis   r4,0,ADDR_08MB@h
        ori     r4,r4,ADDR_08MB@l
        stw     r3,0x00(r4)            // store magic at 8MB
        addis   r3,0,MAGIC2@h
       	ori	r3,r3,MAGIC2@l
        addis   r4,0,ADDR_16MB@h
        ori     r4,r4,ADDR_16MB@l
        stw     r3,0x00(r4)            // store magic at 16MB
        addis   r3,0,MAGIC3@h
       	ori	r3,r3,MAGIC3@l
        addis   r4,0,ADDR_32MB@h
        ori     r4,r4,ADDR_32MB@l
        stw     r3,0x00(r4)            // store magic at 32MB

        addis   r3,0,MAGIC0@h
       	ori	r3,r3,MAGIC0@l
        addis   r4,0,ADDR_ZERO@h
        ori     r4,r4,ADDR_ZERO@l
        lwz     r5,0x00(r4)            // load from 0
        cmplw   0,r3,r5
        bne     ..chk_32mb
        addis   r3,0,MAGIC1@h
       	ori	r3,r3,MAGIC1@l
        addis   r4,0,ADDR_08MB@h
        ori     r4,r4,ADDR_08MB@l
        lwz     r5,0x00(r4)            // load from 8mb
        cmplw   0,r3,r5
        bne     ..chk_32mb
        addis   r3,0,MAGIC2@h
       	ori	r3,r3,MAGIC2@l
        addis   r4,0,ADDR_16MB@h
        ori     r4,r4,ADDR_16MB@l
        lwz     r5,0x00(r4)            // load from 8mb
        beq     ..sdram_done

..chk_32mb:
        //-------------------------------------------------------------------
        // Disable memory controller.
        //-------------------------------------------------------------------
        addi    r4,0,mem_mcopt1
        mtdcr   memcfga,r4
        addis   r4,0,0x0000             // set DC_EN=0
        ori     r4,r4,0x0000
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4)
        //-------------------------------------------------------------------
        addi    r4,0,mem_mb0cf
        mtdcr   memcfga,r4
        addis   r4,0,0x0006
        ori     r4,r4,0x2001
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Set memory controller options reg, MCOPT1.
	// Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
	// read/prefetch.
        //-------------------------------------------------------------------
        addi    r4,0,mem_mcopt1
        mtdcr   memcfga,r4
        addis   r4,0,0x8080             // set DC_EN=1
        ori     r4,r4,0x0000
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Wait some time
        //-------------------------------------------------------------------
        addis   r3,0,0x001E
        ori     r3,r3,0x8480          // ensure 10msec have passed since reset
        mtctr   r3
..spinlp4:
        bdnz    ..spinlp4                // spin loop
        
        //-------------------------------------------------------------------
        // Test if 32MByte is ok.
        //-------------------------------------------------------------------
        addis   r3,0,MAGIC0@h
       	ori	r3,r3,MAGIC0@l
        addis   r4,0,ADDR_ZERO@h
        ori     r4,r4,ADDR_ZERO@l
        stw     r3,0x00(r4)            // store magic at 0
        addis   r3,0,MAGIC1@h
       	ori	r3,r3,MAGIC1@l
        addis   r4,0,ADDR_400@h
        ori     r4,r4,ADDR_400@l
        stw     r3,0x00(r4)            // store magic at 0x400
        addis   r3,0,MAGIC2@h
       	ori	r3,r3,MAGIC2@l
        addis   r4,0,ADDR_08MB@h
        ori     r4,r4,ADDR_08MB@l
        stw     r3,0x00(r4)            // store magic at 8MB
        addis   r3,0,MAGIC3@h
       	ori	r3,r3,MAGIC3@l
        addis   r4,0,ADDR_16MB@h
        ori     r4,r4,ADDR_16MB@l
        stw     r3,0x00(r4)            // store magic at 16MB

        addis   r3,0,MAGIC0@h
       	ori	r3,r3,MAGIC0@l
        addis   r4,0,ADDR_ZERO@h
        ori     r4,r4,ADDR_ZERO@l
        lwz     r5,0x00(r4)            // load from 0
        cmplw   0,r3,r5
        bne     ..chk_16mb
        addis   r3,0,MAGIC1@h
       	ori	r3,r3,MAGIC1@l
        addis   r4,0,ADDR_400@h
        ori     r4,r4,ADDR_400@l
        lwz     r5,0x00(r4)            // load from 0x400
        cmplw   0,r3,r5
        bne     ..chk_16mb
        addis   r3,0,MAGIC2@h
       	ori	r3,r3,MAGIC2@l
        addis   r4,0,ADDR_08MB@h
        ori     r4,r4,ADDR_08MB@l
        lwz     r5,0x00(r4)            // load from 8mb
        cmplw   0,r3,r5
        beq     ..sdram_done
        
..chk_16mb:
        //-------------------------------------------------------------------
        // Disable memory controller.
        //-------------------------------------------------------------------
        addi    r4,0,mem_mcopt1
        mtdcr   memcfga,r4
        addis   r4,0,0x0000             // set DC_EN=0
        ori     r4,r4,0x0000
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // 16 MB is left.
        // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
        //-------------------------------------------------------------------
        addi    r4,0,mem_mb0cf
        mtdcr   memcfga,r4
        addis   r4,0,0x0004
        ori     r4,r4,0x6001
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Set memory controller options reg, MCOPT1.
	// Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
	// read/prefetch.
        //-------------------------------------------------------------------
        addi    r4,0,mem_mcopt1
        mtdcr   memcfga,r4
        addis   r4,0,0x8080             // set DC_EN=1
        ori     r4,r4,0x0000
        mtdcr   memcfgd,r4

        //-------------------------------------------------------------------
        // Wait some time
        //-------------------------------------------------------------------
        addis   r3,0,0x001E
        ori     r3,r3,0x8480          // ensure 10msec have passed since reset
        mtctr   r3
..spinlp5:
        bdnz    ..spinlp5                // spin loop
        
..sdram_done:
        mtlr    r31                     // restore lr
        blr