📄 fifoctlr_ic.vhd
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----------------------------------------------------------------------------- ---- Module : fifoctlr_ic.vhd Last Update: 07/14/00 ---- ---- Description : FIFO controller top level. ---- Implements a 511x8 FIFO with independent read/write ---- clocks. ---- ---- The following VHDL code implements a 511x8 FIFO in a Virtex ---- device. The inputs are a Read Clock and Read Enable, a Write Clock -- -- and Write Enable, Write Data, and a FIFO_gsr signal as an initial ---- reset. The outputs are Read Data, Full, Empty, and the FIFOstatus ---- outputs, which indicate roughly how full the FIFO is. ---- ---- Designer : Nick Camilleri ---- ---- Company : Xilinx, Inc. ---- ---- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY ---- WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY ---- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR ---- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. ---- THEY ARE ONLY INTENDED TO BE USED BY XILINX ---- CUSTOMERS, AND WITHIN XILINX DEVICES. ---- ---- Copyright (c) 2000 Xilinx, Inc. ---- All rights reserved ---- -----------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;-- synthesis translate_offLibrary unisim;use unisim.Vcomponents.all;-- synthesis translate_onentity fifoctlr_ic is port (read_clock_in: IN std_logic; write_clock_in: IN std_logic; read_enable_in: IN std_logic; write_enable_in: IN std_logic; fifo_gsr_in: IN std_logic; write_data_in: IN std_logic_vector(7 downto 0); read_data_out: OUT std_logic_vector(7 downto 0); full_out: OUT std_logic; empty_out: OUT std_logic; fifostatus_out: OUT std_logic_vector(3 downto 0));END fifoctlr_ic;architecture fifoctlr_ic_hdl of fifoctlr_ic is signal read_clock: std_logic; signal write_clock: std_logic; signal read_enable: std_logic; signal write_enable: std_logic; signal fifo_gsr: std_logic; signal read_data: std_logic_vector(7 downto 0); signal write_data: std_logic_vector(7 downto 0); signal full: std_logic; signal empty: std_logic; signal read_addr: std_logic_vector(8 downto 0); signal read_addrgray: std_logic_vector(8 downto 0); signal read_nextgray: std_logic_vector(8 downto 0); signal read_lastgray: std_logic_vector(8 downto 0); signal write_addr: std_logic_vector(8 downto 0); signal write_addrgray: std_logic_vector(8 downto 0); signal write_nextgray: std_logic_vector(8 downto 0); signal fifostatus: std_logic_vector(8 downto 0); signal read_allow: std_logic; signal write_allow: std_logic; signal empty_allow: std_logic; signal full_allow: std_logic; signal ecomp: std_logic_vector(8 downto 0); signal fcomp: std_logic_vector(8 downto 0); signal emuxcyo: std_logic_vector(8 downto 0); signal fmuxcyo: std_logic_vector(8 downto 0); signal emptyg: std_logic; signal fullg: std_logic; signal read_truegray: std_logic_vector(8 downto 0); signal rag_writesync: std_logic_vector(8 downto 0); signal ra_writesync: std_logic_vector(8 downto 0); signal write_addrr: std_logic_vector(8 downto 0); signal xorout: std_logic_vector(1 downto 0); signal gnd_bus: std_logic_vector(7 downto 0); signal gnd: std_logic; signal pwr: std_logic; component BUFGP port ( I: IN std_logic; O: OUT std_logic);END component; component MUXCY_L port ( DI: IN std_logic; CI: IN std_logic; S: IN std_logic; LO: OUT std_logic);END component; component RAMB4_S8_S8 port ( ADDRA: IN std_logic_vector(8 downto 0); ADDRB: IN std_logic_vector(8 downto 0); DIA: IN std_logic_vector(7 downto 0); DIB: IN std_logic_vector(7 downto 0); WEA: IN std_logic; WEB: IN std_logic; CLKA: IN std_logic; CLKB: IN std_logic; RSTA: IN std_logic; RSTB: IN std_logic; ENA: IN std_logic; ENB: IN std_logic; DOA: OUT std_logic_vector(7 downto 0); DOB: OUT std_logic_vector(7 downto 0));END component; BEGIN read_enable <= read_enable_in; write_enable <= write_enable_in; fifo_gsr <= fifo_gsr_in; write_data <= write_data_in; read_data_out <= read_data; full_out <= full; empty_out <= empty; fifostatus_out <= fifostatus(8 downto 5); gnd_bus <= "00000000"; gnd <= '0'; pwr <= '1';---------------------------------------------------------------------------- ---- Global input clock buffers are instantianted for both the read_clock ---- and the write_clock, to avoid skew problems. ---- ----------------------------------------------------------------------------gclk1: BUFGP port map (I => read_clock_in, O => read_clock);gclk2: BUFGP port map (I => write_clock_in, O => write_clock);---------------------------------------------------------------------------- ---- Block RAM instantiation for FIFO. Module is 512x8, of which one ---- address location is sacrificed for the overall speed of the design. ---- ----------------------------------------------------------------------------bram1: RAMB4_S8_S8 port map (ADDRA => read_addr, ADDRB => write_addr, DIA => gnd_bus, DIB => write_data, WEA => gnd, WEB => pwr, CLKA => read_clock, CLKB => write_clock, RSTA => gnd, RSTB => gnd, ENA => read_allow, ENB => write_allow, DOA => read_data ); ------------------------------------------------------------------ ---- Allow flags determine whether FIFO control logic can ---- operate. If read_enable is driven high, and the FIFO is ---- not Empty, then Reads are allowed. Similarly, if the ---- write_enable signal is high, and the FIFO is not Full, ---- then Writes are allowed. ---- ------------------------------------------------------------------read_allow <= (read_enable AND NOT empty);write_allow <= (write_enable AND NOT full);full_allow <= (full OR write_enable);empty_allow <= (empty OR read_enable); ----------------------------------------------------------------- ---- Empty flag is set on fifo_gsr (initial), or when gray ---- code counters are equal, or when there is one word in ---- the FIFO, and a Read operation is about to be performed. ---- -----------------------------------------------------------------proc1: PROCESS (read_clock, fifo_gsr)BEGIN IF (fifo_gsr = '1') THEN empty <= '1'; ELSIF (read_clock'EVENT AND read_clock = '1') THEN IF (empty_allow = '1') THEN empty <= emptyg; END IF; END IF;END PROCESS proc1; ----------------------------------------------------------------- ---- Full flag is set on fifo_gsr (initial, but it is cleared ---- on the first valid write_clock edge after fifo_gsr is ---- de-asserted), or when Gray-code counters are one away ---- from being equal (the Write Gray-code address is equal ---- to the Last Read Gray-code address), or when the Next ---- Write Gray-code address is equal to the Last Read Gray- ---- code address, and a Write operation is about to be ---- performed. ---- -----------------------------------------------------------------proc2: PROCESS (write_clock, fifo_gsr)BEGIN IF (fifo_gsr = '1') THEN full <= '1'; ELSIF (write_clock'EVENT AND write_clock = '1') THEN IF (full_allow = '1') THEN full <= fullg; END IF; END IF;END PROCESS proc2; ------------------------------------------------------------------ ---- Generation of Read address pointers. The primary one is ---- binary (read_addr), and the Gray-code derivatives are ---- generated via pipelining the binary-to-Gray-code result. ---- The initial values are important, so they're in sequence. ---- ---- Grey-code addresses are used so that the registered ---- Full and Empty flags are always clean, and never in an ---- unknown state due to the asynchonous relationship of the ---- Read and Write clocks. In the worst case scenario, Full ---- and Empty would simply stay active one cycle longer, but ---- it would not generate an error or give false values. ---- ------------------------------------------------------------------proc3: PROCESS (read_clock, fifo_gsr)BEGIN IF (fifo_gsr = '1') THEN read_addr <= "000000000"; ELSIF (read_clock'EVENT AND read_clock = '1') THEN IF (read_allow = '1') THEN read_addr <= read_addr + 1; END IF; END IF;END PROCESS proc3; proc4: PROCESS (read_clock, fifo_gsr)BEGIN IF (fifo_gsr = '1') THEN read_nextgray <= "100000000"; ELSIF (read_clock'EVENT AND read_clock = '1') THEN IF (read_allow = '1') THEN read_nextgray(8) <= read_addr(8); read_nextgray(7) <= read_addr(8) XOR read_addr(7); read_nextgray(6) <= read_addr(7) XOR read_addr(6); read_nextgray(5) <= read_addr(6) XOR read_addr(5); read_nextgray(4) <= read_addr(5) XOR read_addr(4); read_nextgray(3) <= read_addr(4) XOR read_addr(3); read_nextgray(2) <= read_addr(3) XOR read_addr(2);⌨️ 快捷键说明
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