fifoctlr_ic_tb.vhd

fifo vhdl源程序

LIBRARY  ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

LIBRARY  unisim;
USE unisim.Vcomponents.all;

LIBRARY ieee;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY tb_ic IS
END tb_ic;

ARCHITECTURE tb_ic_arch OF tb_ic IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 93
FILE RESULTS: TEXT IS OUT "results.txt";
	COMPONENT fifoctlr_ic
		PORT (
			read_clock_in:   IN  std_logic;
         write_clock_in:  IN  std_logic;
         read_enable_in:  IN  std_logic;
         write_enable_in: IN  std_logic;
         fifo_gsr_in:     IN  std_logic;
         write_data_in:   IN  std_logic_vector(7 downto 0);
         read_data_out:   OUT std_logic_vector(7 downto 0);
         full_out:        OUT std_logic;
         empty_out:       OUT std_logic;
         fifostatus_out:  OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

	SIGNAL read_clock_in : std_logic;
	SIGNAL write_clock_in : std_logic;
	SIGNAL read_enable_in : std_logic;
	SIGNAL write_enable_in : std_logic;
	SIGNAL write_data_in : std_logic_vector (7 DOWNTO 0);
	SIGNAL fifo_gsr_in : std_logic;
	SIGNAL read_data_out : std_logic_vector (7 DOWNTO 0);
	SIGNAL full_out : std_logic;
	SIGNAL empty_out : std_logic;
	SIGNAL fifostatus_out : std_logic_vector (3 DOWNTO 0);

BEGIN
	UUT : fifoctlr_ic
	PORT MAP (
		read_clock_in => read_clock_in,
		write_clock_in => write_clock_in,
		read_enable_in => read_enable_in,
		write_enable_in => write_enable_in,
		write_data_in => write_data_in,
		fifo_gsr_in => fifo_gsr_in,
		read_data_out => read_data_out,
		full_out => full_out,
		empty_out => empty_out,
		fifostatus_out => fifostatus_out
	);

	PROCESS -- write_clock_in 50Mhz process
	BEGIN
		CLOCK_LOOP : LOOP
		write_clock_in <= transport '0';
		WAIT FOR 8 ns;
		write_clock_in <= transport '1';
		WAIT FOR 12 ns;
		WAIT FOR 8 ns;
		write_clock_in <= transport '0';
		WAIT FOR 12 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

   PROCESS -- read_clock_in 15Mhz process
	BEGIN
		CLOCK_LOOP : LOOP
		read_clock_in <= transport '0';
		WAIT FOR 26.8 ns;
		read_clock_in <= transport '1';
		WAIT FOR 40.2 ns;
		WAIT FOR 26.8 ns;
		read_clock_in <= transport '0';
		WAIT FOR 40.2 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_read_data_out(
			next_read_data_out : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 512);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			-- From ModelSim's menu do Options->Compile.  Select the VHDL tab.  Check "Use explicit declarations only".
			IF (read_data_out /= next_read_data_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns read_data_out="));
				write(TX_LOC, read_data_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_read_data_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_full_out(
			next_full_out : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 512);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			-- From ModelSim's menu do Options->Compile.  Select the VHDL tab.  Check "Use explicit declarations only".
			IF (full_out /= next_full_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns full_out="));
				write(TX_LOC, full_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_full_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_empty_out(
			next_empty_out : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 512);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			-- From ModelSim's menu do Options->Compile.  Select the VHDL tab.  Check "Use explicit declarations only".
			IF (empty_out /= next_empty_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns empty_out="));
				write(TX_LOC, empty_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_empty_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_fifostatus_out(
			next_fifostatus_out : std_logic_vector (3 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 512);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			-- From ModelSim's menu do Options->Compile.  Select the VHDL tab.  Check "Use explicit declarations only".
			IF (fifostatus_out /= next_fifostatus_out) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns fifostatus_out="));
				write(TX_LOC, fifostatus_out);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_fifostatus_out);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		read_enable_in <= transport '0';
		write_enable_in <= transport '0';
		write_data_in <= transport std_logic_vector'("00000000"); --0
		fifo_gsr_in <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=20 ns
		CHECK_full_out('1',20);
		CHECK_empty_out('1',20);
		CHECK_fifostatus_out("0000",20); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=120 ns
		fifo_gsr_in <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=140 ns
		CHECK_full_out('0',140);
		-- --------------------
		WAIT FOR 20 ns; -- Time=160 ns
		write_enable_in <= transport '1';
		write_data_in <= transport std_logic_vector'("00000000"); --0
		fifo_gsr_in <= transport '0';
		-- --------------------
		WAIT FOR 40 ns; -- Time=200 ns
		write_enable_in <= transport '1';
		write_data_in <= transport std_logic_vector'("00000001"); --1
		fifo_gsr_in <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=220 ns
		CHECK_empty_out('1',220);
		-- --------------------
		WAIT FOR 20 ns; -- Time=240 ns
		write_data_in <= transport std_logic_vector'("00000010"); --2
		-- --------------------
		WAIT FOR 40 ns; -- Time=280 ns
		write_data_in <= transport std_logic_vector'("00000011"); --3
		-- --------------------
		WAIT FOR 40 ns; -- Time=320 ns
		write_data_in <= transport std_logic_vector'("00000100"); --4
		CHECK_empty_out('0',220);
		-- --------------------
		WAIT FOR 40 ns; -- Time=360 ns
		write_data_in <= transport std_logic_vector'("00000101"); --5
		-- --------------------
		WAIT FOR 40 ns; -- Time=400 ns
		write_data_in <= transport std_logic_vector'("00000110"); --6
		-- --------------------
		WAIT FOR 40 ns; -- Time=440 ns
		write_data_in <= transport std_logic_vector'("00000111"); --7
		-- --------------------
		WAIT FOR 40 ns; -- Time=480 ns
		write_data_in <= transport std_logic_vector'("00001000"); --8
		-- --------------------
		WAIT FOR 40 ns; -- Time=520 ns
		write_data_in <= transport std_logic_vector'("00001001"); --9
		-- --------------------
		WAIT FOR 40 ns; -- Time=560 ns
		write_data_in <= transport std_logic_vector'("00001010"); --A
		-- --------------------
		WAIT FOR 40 ns; -- Time=600 ns
		write_data_in <= transport std_logic_vector'("00001011"); --B
		-- --------------------
		WAIT FOR 40 ns; -- Time=640 ns
		write_data_in <= transport std_logic_vector'("00001100"); --C
		-- --------------------
		WAIT FOR 40 ns; -- Time=680 ns
		write_data_in <= transport std_logic_vector'("00001101"); --D
		-- --------------------
		WAIT FOR 40 ns; -- Time=720 ns
		write_data_in <= transport std_logic_vector'("00001110"); --E
		-- --------------------
		WAIT FOR 40 ns; -- Time=760 ns
		write_data_in <= transport std_logic_vector'("00001111"); --F
		-- --------------------
		WAIT FOR 40 ns; -- Time=800 ns
		write_data_in <= transport std_logic_vector'("00010000"); --10
		-- --------------------
		WAIT FOR 40 ns; -- Time=840 ns
		write_data_in <= transport std_logic_vector'("00010001"); --11
		-- --------------------
		WAIT FOR 40 ns; -- Time=880 ns
		write_data_in <= transport std_logic_vector'("00010010"); --12
		-- --------------------
		WAIT FOR 40 ns; -- Time=920 ns
		write_data_in <= transport std_logic_vector'("00010011"); --13
		-- --------------------
		WAIT FOR 40 ns; -- Time=960 ns
		read_enable_in <= transport '1';
		write_enable_in <= transport '0';
		-- --------------------
		WAIT FOR 190 ns; -- Time=1150 ns
		CHECK_read_data_out("00000001",1150); --1
		-- --------------------
		WAIT FOR 130 ns; -- Time=1280 ns
		CHECK_read_data_out("00000010",1280); --2
		-- --------------------
		WAIT FOR 130 ns; -- Time=1410 ns
		CHECK_read_data_out("00000011",1410); --3
		-- --------------------
		WAIT FOR 130 ns; -- Time=1540 ns
		CHECK_read_data_out("00000100",1540); --4
		-- --------------------
		WAIT FOR 130 ns; -- Time=1670 ns
		CHECK_read_data_out("00000101",1670); --5
		-- --------------------
		WAIT FOR 130 ns; -- Time=1800 ns
		CHECK_read_data_out("00000110",1800); --6
		-- --------------------
		WAIT FOR 130 ns; -- Time=1930 ns
		CHECK_read_data_out("00000111",1930); --7
		-- --------------------
		WAIT FOR 130 ns; -- Time=2060 ns
		CHECK_read_data_out("00001000",2060); --8
		-- --------------------
		WAIT FOR 130 ns; -- Time=2190 ns
		CHECK_read_data_out("00001001",2190); --9
		-- --------------------
		WAIT FOR 130 ns; -- Time=2320 ns
		CHECK_read_data_out("00001010",2320); --A
		-- --------------------
		WAIT FOR 130 ns; -- Time=2450 ns
		CHECK_read_data_out("00001011",2450); --B
		-- --------------------
		WAIT FOR 140 ns; -- Time=2580 ns
		CHECK_read_data_out("00001100",2580); --C
		-- --------------------
		WAIT FOR 130 ns; -- Time=2710 ns
		CHECK_read_data_out("00001101",2710); --D
		-- --------------------
		WAIT FOR 140 ns; -- Time=2860 ns
		CHECK_read_data_out("00001110",2860); --E
		-- --------------------
		WAIT FOR 130 ns; -- Time=2990 ns
		CHECK_read_data_out("00001111",2990); --F
		-- --------------------
		WAIT FOR 130 ns; -- Time=3120 ns
		CHECK_read_data_out("00010000",3120); --10
		-- --------------------
		WAIT FOR 140 ns; -- Time=3250 ns
		CHECK_read_data_out("00010001",3250); --11
		-- --------------------
		WAIT FOR 130 ns; -- Time=3380 ns
		CHECK_read_data_out("00010010",3380); --12
		-- --------------------
		WAIT FOR 140 ns; -- Time=3520 ns
		CHECK_read_data_out("00010011",3520); --13
		-- --------------------
		WAIT FOR 130 ns; -- Time=3650 ns
		CHECK_empty_out('1',3650);
		-- --------------------
		WAIT FOR 168 ns; -- Time=3818 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			write(TX_OUT,string'("No errors or warnings"));
			writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			write(TX_OUT, TX_ERROR);
			write(TX_OUT, string'(
				" errors found in simulation"));
			writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END tb_ic_arch;

CONFIGURATION fifoctlr_cc_cfg OF tb_ic IS
	FOR tb_ic_arch
	END FOR;
END fifoctlr_cc_cfg;