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fifo vhdl源程序

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Description: This design describes the implementation of FIFO in Virtex FPGAs.
For a full functional description see Application Note 131:
	 http://www.xilinx.com/xapp/xapp131.pdf

Design Type: ISE (chip v50 BG256 -6)

Source Files:

fifoctlr_cc - FIFO controller top level. Implements a 511x8 FIFO with common 
	      read/write clocks. 

fifoctlr_ic - FIFO controller top level. Implements a 511x8 FIFO with independent 
	      read/write clocks.

Inputs:
* read_clock_in  
* write_clock_in 
* read_enable_in 
* write_enable_in 
* fifo_gsr_in 
* write_data_in[7;0] 

Outputs:
* read_data_out[7:0] 
* full_out 
* empty_out 
* fifostatus_out[3:0] 

Simulation:
Requires the following simulation libraries:
	Unisims
	Simprims

Behavioural and RTL Simulation are done using VHDL Testbench files (fifoctlr_cc_tb.vhd and fifoctlr_ic_tb.vhd).


NOTE: If you are trying to run this example in a read-only location,    
the design hierachy will not display properly. Please copy the example  
project to a new location by using either Project Save As... from the File menu
pulldown in ISE or some other method of your choice. Copy the example to a location
where you have write permissions and the hiearchy will display properly. 


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