fifo_vhd.npl

来自「fifo vhdl源程序」· NPL 代码 · 共 32 行

JDF G
// Converted from an earlier version by Project Navigator version 5
PROJECT fifoctrl_vhd
DESIGN fifo_vhd Normal
DEVFAM virtex
DEVFAMTIME 1016217353
DEVICE xcv50
DEVICETIME 1016217353
DEVPKG bg256
DEVPKGTIME 1016217353
DEVSPEED -6
DEVSPEEDTIME 1016217353
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
STIMULUS fifoctlr_ic_tb.vhd Normal
STIMULUS fifoctlr_cc_tb.vhd Normal
DOCUMENT readme
MODULE fifoctlr_ic.vhd
MODSTYLE fifoctlr_ic Normal
MODULE fifoctlr_cc.vhd
MODSTYLE fifoctlr_cc Normal
DEPASSOC fifoctlr_cc fifoctlr_cc.ucf SYSTEM
[STRATEGY-LIST]
Normal=True
p_ModelSimSimRunTime=False