sram_2.fit.smsg

FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序

    Warning: Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DREQ0" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DREQ1" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_FSPEED" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_INT0" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_INT1" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_LSPEED" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_RD_N" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_RST_N" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_WR_N" is assigned to location or region, but does not exist in design
    Warning: Node "PS2_CLK" is assigned to location or region, but does not exist in design
    Warning: Node "PS2_DAT" is assigned to location or region, but does not exist in design
    Warning: Node "SD_CLK" is assigned to location or region, but does not exist in design
    Warning: Node "SD_CMD" is assigned to location or region, but does not exist in design
    Warning: Node "SD_DAT" is assigned to location or region, but does not exist in design
    Warning: Node "SD_DAT3" is assigned to location or region, but does not exist in design
    Warning: Node "TCK" is assigned to location or region, but does not exist in design
    Warning: Node "TCS" is assigned to location or region, but does not exist in design
    Warning: Node "TDI" is assigned to location or region, but does not exist in design
    Warning: Node "TDO" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_HS" is assigned to location or region, but does not exist in design
    Warning: Node "TD_RESET" is assigned to location or region, but does not exist in design
    Warning: Node "TD_VS" is assigned to location or region, but does not exist in design
    Warning: Node "UART_RXD" is assigned to location or region, but does not exist in design
    Warning: Node "UART_TXD" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_BLANK" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[0]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[1]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[2]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[3]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[4]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[5]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[6]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[7]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[8]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[9]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_CLK" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[0]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[1]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[2]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[3]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[4]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[5]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[6]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[7]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[8]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[9]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_HS" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[0]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[1]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[2]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[3]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[4]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[5]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[6]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[7]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[8]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[9]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_SYNC" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_VS" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 5.769 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y2; Fanout = 5; REG Node = 'tmp_addr[1]'
    Info: 2: + IC(0.203 ns) + CELL(0.420 ns) = 0.623 ns; Loc. = LAB_X17_Y2; Fanout = 1; COMB Node = 'LessThan1~299'
    Info: 3: + IC(0.603 ns) + CELL(0.410 ns) = 1.636 ns; Loc. = LAB_X17_Y1; Fanout = 1; COMB Node = 'LessThan1~300'
    Info: 4: + IC(0.415 ns) + CELL(0.150 ns) = 2.201 ns; Loc. = LAB_X17_Y1; Fanout = 3; COMB Node = 'LessThan1~301'
    Info: 5: + IC(0.145 ns) + CELL(0.420 ns) = 2.766 ns; Loc. = LAB_X17_Y1; Fanout = 2; COMB Node = 'always0~0'
    Info: 6: + IC(0.890 ns) + CELL(0.393 ns) = 4.049 ns; Loc. = LAB_X17_Y2; Fanout = 2; COMB Node = 'tmp_addr[0]~219'
    Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 4.120 ns; Loc. = LAB_X17_Y2; Fanout = 2; COMB Node = 'tmp_addr[1]~220'
    Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 4.191 ns; Loc. = LAB_X17_Y2; Fanout = 2; COMB Node = 'tmp_addr[2]~221'
    Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 4.262 ns; Loc. = LAB_X17_Y2; Fanout = 2; COMB Node = 'tmp_addr[3]~222'
    Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 4.333 ns; Loc. = LAB_X17_Y2; Fanout = 2; COMB Node = 'tmp_addr[4]~223'
    Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 4.404 ns; Loc. = LAB_X17_Y2; Fanout = 2; COMB Node = 'tmp_addr[5]~224'
    Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 4.475 ns; Loc. = LAB_X17_Y2; Fanout = 2; COMB Node = 'tmp_addr[6]~225'
    Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 4.546 ns; Loc. = LAB_X17_Y2; Fanout = 2; COMB Node = 'tmp_addr[7]~226'
    Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 4.617 ns; Loc. = LAB_X17_Y2; Fanout = 2; COMB Node = 'tmp_addr[8]~227'
    Info: 15: + IC(0.090 ns) + CELL(0.071 ns) = 4.778 ns; Loc. = LAB_X17_Y1; Fanout = 2; COMB Node = 'tmp_addr[9]~228'
    Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 4.849 ns; Loc. = LAB_X17_Y1; Fanout = 2; COMB Node = 'tmp_addr[10]~229'
    Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 4.920 ns; Loc. = LAB_X17_Y1; Fanout = 2; COMB Node = 'tmp_addr[11]~230'
    Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 4.991 ns; Loc. = LAB_X17_Y1; Fanout = 2; COMB Node = 'tmp_addr[12]~231'
    Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 5.062 ns; Loc. = LAB_X17_Y1; Fanout = 2; COMB Node = 'tmp_addr[13]~232'
    Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 5.133 ns; Loc. = LAB_X17_Y1; Fanout = 2; COMB Node = 'tmp_addr[14]~233'
    Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 5.204 ns; Loc. = LAB_X17_Y1; Fanout = 2; COMB Node = 'tmp_addr[15]~234'
    Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 5.275 ns; Loc. = LAB_X17_Y1; Fanout = 1; COMB Node = 'tmp_addr[16]~235'
    Info: 23: + IC(0.000 ns) + CELL(0.410 ns) = 5.685 ns; Loc. = LAB_X17_Y1; Fanout = 1; COMB Node = 'tmp_addr[17]~171'
    Info: 24: + IC(0.000 ns) + CELL(0.084 ns) = 5.769 ns; Loc. = LAB_X17_Y1; Fanout = 3; REG Node = 'tmp_addr[17]'
    Info: Total cell delay = 3.423 ns ( 59.33 % )
    Info: Total interconnect delay = 2.346 ns ( 40.67 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X11_Y0 to location X21_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 94 output pins without output pin load capacitance assignment
    Info: Pin "HEX0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HEX0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis