sram_2.tan.qmsg

FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序

{ "Info" "ITAN_NO_REG2REG_EXIST" "CLOCK_50 " "Info: No valid register-to-register data paths exist for clock \"CLOCK_50\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 register tmp_addr\[7\] register SRAM_DQ\[7\]~reg0 555 ps " "Info: Minimum slack time is 555 ps for clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" between source register \"tmp_addr\[7\]\" and destination register \"SRAM_DQ\[7\]~reg0\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.571 ns + Shortest register register " "Info: + Shortest register to register delay is 0.571 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmp_addr\[7\] 1 REG LCFF_X17_Y2_N29 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y2_N29; Fanout = 5; REG Node = 'tmp_addr\[7\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmp_addr[7] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.338 ns) + CELL(0.149 ns) 0.487 ns SRAM_DQ\[7\]~reg0feeder 2 COMB LCCOMB_X17_Y2_N12 1 " "Info: 2: + IC(0.338 ns) + CELL(0.149 ns) = 0.487 ns; Loc. = LCCOMB_X17_Y2_N12; Fanout = 1; COMB Node = 'SRAM_DQ\[7\]~reg0feeder'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.487 ns" { tmp_addr[7] SRAM_DQ[7]~reg0feeder } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.571 ns SRAM_DQ\[7\]~reg0 3 REG LCFF_X17_Y2_N13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.571 ns; Loc. = LCFF_X17_Y2_N13; Fanout = 1; REG Node = 'SRAM_DQ\[7\]~reg0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { SRAM_DQ[7]~reg0feeder SRAM_DQ[7]~reg0 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.233 ns ( 40.81 % ) " "Info: Total cell delay = 0.233 ns ( 40.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.338 ns ( 59.19 % ) " "Info: Total interconnect delay = 0.338 ns ( 59.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { tmp_addr[7] SRAM_DQ[7]~reg0feeder SRAM_DQ[7]~reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "0.571 ns" { tmp_addr[7] SRAM_DQ[7]~reg0feeder SRAM_DQ[7]~reg0 } { 0.000ns 0.338ns 0.000ns } { 0.000ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.358 ns " "Info: + Latch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 100.000 ns -2.358 ns  50 " "Info: Clock period of Destination clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" is 100.000 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 100.000 ns -2.358 ns  50 " "Info: Clock period of Source clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" is 100.000 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 destination 2.666 ns + Longest register " "Info: + Longest clock path from clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" to destination register is 2.666 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 82 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 82; COMB Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.537 ns) 2.666 ns SRAM_DQ\[7\]~reg0 3 REG LCFF_X17_Y2_N13 1 " "Info: 3: + IC(1.038 ns) + CELL(0.537 ns) = 2.666 ns; Loc. = LCFF_X17_Y2_N13; Fanout = 1; REG Node = 'SRAM_DQ\[7\]~reg0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.575 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl SRAM_DQ[7]~reg0 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.14 % ) " "Info: Total cell delay = 0.537 ns ( 20.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.129 ns ( 79.86 % ) " "Info: Total interconnect delay = 2.129 ns ( 79.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl SRAM_DQ[7]~reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl SRAM_DQ[7]~reg0 } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 source 2.666 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" to source register is 2.666 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 82 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 82; COMB Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.537 ns) 2.666 ns tmp_addr\[7\] 3 REG LCFF_X17_Y2_N29 5 " "Info: 3: + IC(1.038 ns) + CELL(0.537 ns) = 2.666 ns; Loc. = LCFF_X17_Y2_N29; Fanout = 5; REG Node = 'tmp_addr\[7\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.575 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[7] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.14 % ) " "Info: Total cell delay = 0.537 ns ( 20.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.129 ns ( 79.86 % ) " "Info: Total interconnect delay = 2.129 ns ( 79.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[7] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[7] } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl SRAM_DQ[7]~reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl SRAM_DQ[7]~reg0 } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[7] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[7] } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl SRAM_DQ[7]~reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl SRAM_DQ[7]~reg0 } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[7] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[7] } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { tmp_addr[7] SRAM_DQ[7]~reg0feeder SRAM_DQ[7]~reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "0.571 ns" { tmp_addr[7] SRAM_DQ[7]~reg0feeder SRAM_DQ[7]~reg0 } { 0.000ns 0.338ns 0.000ns } { 0.000ns 0.149ns 0.084ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl SRAM_DQ[7]~reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl SRAM_DQ[7]~reg0 } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[7] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.666 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[7] } { 0.000ns 1.091ns 1.038ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}