sram_2.tan.qmsg

FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 register tmp_addr\[15\] register tmp_addr\[17\] 94.368 ns " "Info: Slack time is 94.368 ns for clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" between source register \"tmp_addr\[15\]\" and destination register \"tmp_addr\[17\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "177.56 MHz 5.632 ns " "Info: Fmax is 177.56 MHz (period= 5.632 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "99.786 ns + Largest register register " "Info: + Largest register to register requirement is 99.786 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "100.000 ns + " "Info: + Setup relationship between source and destination is 100.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 97.642 ns " "Info: + Latch edge is 97.642 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 100.000 ns -2.358 ns  50 " "Info: Clock period of Destination clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" is 100.000 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 100.000 ns -2.358 ns  50 " "Info: Clock period of Source clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" is 100.000 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 destination 2.667 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" to destination register is 2.667 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 82 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 82; COMB Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.537 ns) 2.667 ns tmp_addr\[17\] 3 REG LCFF_X17_Y1_N17 3 " "Info: 3: + IC(1.039 ns) + CELL(0.537 ns) = 2.667 ns; Loc. = LCFF_X17_Y1_N17; Fanout = 3; REG Node = 'tmp_addr\[17\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.576 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[17] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.13 % ) " "Info: Total cell delay = 0.537 ns ( 20.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.130 ns ( 79.87 % ) " "Info: Total interconnect delay = 2.130 ns ( 79.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[17] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[17] } { 0.000ns 1.091ns 1.039ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 source 2.667 ns - Longest register " "Info: - Longest clock path from clock \"CLK_10MHZ:M1\|altpll:altpll_component\|_clk0\" to source register is 2.667 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 82 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 82; COMB Node = 'CLK_10MHZ:M1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.537 ns) 2.667 ns tmp_addr\[15\] 3 REG LCFF_X17_Y1_N13 5 " "Info: 3: + IC(1.039 ns) + CELL(0.537 ns) = 2.667 ns; Loc. = LCFF_X17_Y1_N13; Fanout = 5; REG Node = 'tmp_addr\[15\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.576 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[15] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.13 % ) " "Info: Total cell delay = 0.537 ns ( 20.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.130 ns ( 79.87 % ) " "Info: Total interconnect delay = 2.130 ns ( 79.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[15] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[15] } { 0.000ns 1.091ns 1.039ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[17] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[17] } { 0.000ns 1.091ns 1.039ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[15] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[15] } { 0.000ns 1.091ns 1.039ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" {  } { { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[17] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[17] } { 0.000ns 1.091ns 1.039ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[15] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[15] } { 0.000ns 1.091ns 1.039ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.418 ns - Longest register register " "Info: - Longest register to register delay is 5.418 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmp_addr\[15\] 1 REG LCFF_X17_Y1_N13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y1_N13; Fanout = 5; REG Node = 'tmp_addr\[15\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmp_addr[15] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.510 ns) + CELL(0.393 ns) 0.903 ns LessThan1~297 2 COMB LCCOMB_X17_Y1_N22 1 " "Info: 2: + IC(0.510 ns) + CELL(0.393 ns) = 0.903 ns; Loc. = LCCOMB_X17_Y1_N22; Fanout = 1; COMB Node = 'LessThan1~297'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.903 ns" { tmp_addr[15] LessThan1~297 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.150 ns) 1.303 ns LessThan1~298 3 COMB LCCOMB_X17_Y1_N20 1 " "Info: 3: + IC(0.250 ns) + CELL(0.150 ns) = 1.303 ns; Loc. = LCCOMB_X17_Y1_N20; Fanout = 1; COMB Node = 'LessThan1~298'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { LessThan1~297 LessThan1~298 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.437 ns) 2.006 ns LessThan1~301 4 COMB LCCOMB_X17_Y1_N18 3 " "Info: 4: + IC(0.266 ns) + CELL(0.437 ns) = 2.006 ns; Loc. = LCCOMB_X17_Y1_N18; Fanout = 3; COMB Node = 'LessThan1~301'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.703 ns" { LessThan1~298 LessThan1~301 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.262 ns) + CELL(0.149 ns) 2.417 ns always0~0 5 COMB LCCOMB_X17_Y1_N26 2 " "Info: 5: + IC(0.262 ns) + CELL(0.149 ns) = 2.417 ns; Loc. = LCCOMB_X17_Y1_N26; Fanout = 2; COMB Node = 'always0~0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.411 ns" { LessThan1~301 always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.485 ns) 3.625 ns tmp_addr\[0\]~219 6 COMB LCCOMB_X17_Y2_N14 2 " "Info: 6: + IC(0.723 ns) + CELL(0.485 ns) = 3.625 ns; Loc. = LCCOMB_X17_Y2_N14; Fanout = 2; COMB Node = 'tmp_addr\[0\]~219'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.208 ns" { always0~0 tmp_addr[0]~219 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.696 ns tmp_addr\[1\]~220 7 COMB LCCOMB_X17_Y2_N16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 3.696 ns; Loc. = LCCOMB_X17_Y2_N16; Fanout = 2; COMB Node = 'tmp_addr\[1\]~220'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[0]~219 tmp_addr[1]~220 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.767 ns tmp_addr\[2\]~221 8 COMB LCCOMB_X17_Y2_N18 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 3.767 ns; Loc. = LCCOMB_X17_Y2_N18; Fanout = 2; COMB Node = 'tmp_addr\[2\]~221'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[1]~220 tmp_addr[2]~221 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.838 ns tmp_addr\[3\]~222 9 COMB LCCOMB_X17_Y2_N20 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 3.838 ns; Loc. = LCCOMB_X17_Y2_N20; Fanout = 2; COMB Node = 'tmp_addr\[3\]~222'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[2]~221 tmp_addr[3]~222 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.909 ns tmp_addr\[4\]~223 10 COMB LCCOMB_X17_Y2_N22 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 3.909 ns; Loc. = LCCOMB_X17_Y2_N22; Fanout = 2; COMB Node = 'tmp_addr\[4\]~223'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[3]~222 tmp_addr[4]~223 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.980 ns tmp_addr\[5\]~224 11 COMB LCCOMB_X17_Y2_N24 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 3.980 ns; Loc. = LCCOMB_X17_Y2_N24; Fanout = 2; COMB Node = 'tmp_addr\[5\]~224'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[4]~223 tmp_addr[5]~224 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.051 ns tmp_addr\[6\]~225 12 COMB LCCOMB_X17_Y2_N26 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 4.051 ns; Loc. = LCCOMB_X17_Y2_N26; Fanout = 2; COMB Node = 'tmp_addr\[6\]~225'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[5]~224 tmp_addr[6]~225 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.122 ns tmp_addr\[7\]~226 13 COMB LCCOMB_X17_Y2_N28 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 4.122 ns; Loc. = LCCOMB_X17_Y2_N28; Fanout = 2; COMB Node = 'tmp_addr\[7\]~226'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[6]~225 tmp_addr[7]~226 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 4.268 ns tmp_addr\[8\]~227 14 COMB LCCOMB_X17_Y2_N30 2 " "Info: 14: + IC(0.000 ns) + CELL(0.146 ns) = 4.268 ns; Loc. = LCCOMB_X17_Y2_N30; Fanout = 2; COMB Node = 'tmp_addr\[8\]~227'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.146 ns" { tmp_addr[7]~226 tmp_addr[8]~227 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.339 ns tmp_addr\[9\]~228 15 COMB LCCOMB_X17_Y1_N0 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 4.339 ns; Loc. = LCCOMB_X17_Y1_N0; Fanout = 2; COMB Node = 'tmp_addr\[9\]~228'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[8]~227 tmp_addr[9]~228 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.410 ns tmp_addr\[10\]~229 16 COMB LCCOMB_X17_Y1_N2 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 4.410 ns; Loc. = LCCOMB_X17_Y1_N2; Fanout = 2; COMB Node = 'tmp_addr\[10\]~229'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[9]~228 tmp_addr[10]~229 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.481 ns tmp_addr\[11\]~230 17 COMB LCCOMB_X17_Y1_N4 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 4.481 ns; Loc. = LCCOMB_X17_Y1_N4; Fanout = 2; COMB Node = 'tmp_addr\[11\]~230'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[10]~229 tmp_addr[11]~230 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.552 ns tmp_addr\[12\]~231 18 COMB LCCOMB_X17_Y1_N6 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 4.552 ns; Loc. = LCCOMB_X17_Y1_N6; Fanout = 2; COMB Node = 'tmp_addr\[12\]~231'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[11]~230 tmp_addr[12]~231 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.623 ns tmp_addr\[13\]~232 19 COMB LCCOMB_X17_Y1_N8 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 4.623 ns; Loc. = LCCOMB_X17_Y1_N8; Fanout = 2; COMB Node = 'tmp_addr\[13\]~232'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[12]~231 tmp_addr[13]~232 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.694 ns tmp_addr\[14\]~233 20 COMB LCCOMB_X17_Y1_N10 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 4.694 ns; Loc. = LCCOMB_X17_Y1_N10; Fanout = 2; COMB Node = 'tmp_addr\[14\]~233'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[13]~232 tmp_addr[14]~233 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.765 ns tmp_addr\[15\]~234 21 COMB LCCOMB_X17_Y1_N12 2 " "Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 4.765 ns; Loc. = LCCOMB_X17_Y1_N12; Fanout = 2; COMB Node = 'tmp_addr\[15\]~234'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { tmp_addr[14]~233 tmp_addr[15]~234 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 4.924 ns tmp_addr\[16\]~235 22 COMB LCCOMB_X17_Y1_N14 1 " "Info: 22: + IC(0.000 ns) + CELL(0.159 ns) = 4.924 ns; Loc. = LCCOMB_X17_Y1_N14; Fanout = 1; COMB Node = 'tmp_addr\[16\]~235'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { tmp_addr[15]~234 tmp_addr[16]~235 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 5.334 ns tmp_addr\[17\]~171 23 COMB LCCOMB_X17_Y1_N16 1 " "Info: 23: + IC(0.000 ns) + CELL(0.410 ns) = 5.334 ns; Loc. = LCCOMB_X17_Y1_N16; Fanout = 1; COMB Node = 'tmp_addr\[17\]~171'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { tmp_addr[16]~235 tmp_addr[17]~171 } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 5.418 ns tmp_addr\[17\] 24 REG LCFF_X17_Y1_N17 3 " "Info: 24: + IC(0.000 ns) + CELL(0.084 ns) = 5.418 ns; Loc. = LCFF_X17_Y1_N17; Fanout = 3; REG Node = 'tmp_addr\[17\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { tmp_addr[17]~171 tmp_addr[17] } "NODE_NAME" } } { "SRAM_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns ( 62.88 % ) " "Info: Total cell delay = 3.407 ns ( 62.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.011 ns ( 37.12 % ) " "Info: Total interconnect delay = 2.011 ns ( 37.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.418 ns" { tmp_addr[15] LessThan1~297 LessThan1~298 LessThan1~301 always0~0 tmp_addr[0]~219 tmp_addr[1]~220 tmp_addr[2]~221 tmp_addr[3]~222 tmp_addr[4]~223 tmp_addr[5]~224 tmp_addr[6]~225 tmp_addr[7]~226 tmp_addr[8]~227 tmp_addr[9]~228 tmp_addr[10]~229 tmp_addr[11]~230 tmp_addr[12]~231 tmp_addr[13]~232 tmp_addr[14]~233 tmp_addr[15]~234 tmp_addr[16]~235 tmp_addr[17]~171 tmp_addr[17] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.418 ns" { tmp_addr[15] LessThan1~297 LessThan1~298 LessThan1~301 always0~0 tmp_addr[0]~219 tmp_addr[1]~220 tmp_addr[2]~221 tmp_addr[3]~222 tmp_addr[4]~223 tmp_addr[5]~224 tmp_addr[6]~225 tmp_addr[7]~226 tmp_addr[8]~227 tmp_addr[9]~228 tmp_addr[10]~229 tmp_addr[11]~230 tmp_addr[12]~231 tmp_addr[13]~232 tmp_addr[14]~233 tmp_addr[15]~234 tmp_addr[16]~235 tmp_addr[17]~171 tmp_addr[17] } { 0.000ns 0.510ns 0.250ns 0.266ns 0.262ns 0.723ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.150ns 0.437ns 0.149ns 0.485ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.410ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[17] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[17] } { 0.000ns 1.091ns 1.039ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[15] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.667 ns" { CLK_10MHZ:M1|altpll:altpll_component|_clk0 CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl tmp_addr[15] } { 0.000ns 1.091ns 1.039ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.418 ns" { tmp_addr[15] LessThan1~297 LessThan1~298 LessThan1~301 always0~0 tmp_addr[0]~219 tmp_addr[1]~220 tmp_addr[2]~221 tmp_addr[3]~222 tmp_addr[4]~223 tmp_addr[5]~224 tmp_addr[6]~225 tmp_addr[7]~226 tmp_addr[8]~227 tmp_addr[9]~228 tmp_addr[10]~229 tmp_addr[11]~230 tmp_addr[12]~231 tmp_addr[13]~232 tmp_addr[14]~233 tmp_addr[15]~234 tmp_addr[16]~235 tmp_addr[17]~171 tmp_addr[17] } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.418 ns" { tmp_addr[15] LessThan1~297 LessThan1~298 LessThan1~301 always0~0 tmp_addr[0]~219 tmp_addr[1]~220 tmp_addr[2]~221 tmp_addr[3]~222 tmp_addr[4]~223 tmp_addr[5]~224 tmp_addr[6]~225 tmp_addr[7]~226 tmp_addr[8]~227 tmp_addr[9]~228 tmp_addr[10]~229 tmp_addr[11]~230 tmp_addr[12]~231 tmp_addr[13]~232 tmp_addr[14]~233 tmp_addr[15]~234 tmp_addr[16]~235 tmp_addr[17]~171 tmp_addr[17] } { 0.000ns 0.510ns 0.250ns 0.266ns 0.262ns 0.723ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.150ns 0.437ns 0.149ns 0.485ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.410ns 0.084ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}