sram_2.map.rpt
来自「FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序」· RPT 代码 · 共 696 行 · 第 1/4 页
RPT
696 行
; |SRAM_2 ; 73 (73) ; 82 (82) ; 0 ; 0 ; 0 ; 0 ; 117 ; 0 ; |SRAM_2 ;
; |CLK_10MHZ:M1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|CLK_10MHZ:M1 ;
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|CLK_10MHZ:M1|altpll:altpll_component ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+--------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+--------------------------+
; always0~4 ; Merged with always0~1 ;
; always0~6 ; Merged with always0~1 ;
; always0~8 ; Merged with always0~1 ;
; always0~10 ; Merged with always0~1 ;
; always0~12 ; Merged with always0~1 ;
; always0~14 ; Merged with always0~1 ;
; always0~16 ; Merged with always0~1 ;
; always0~18 ; Merged with always0~1 ;
; always0~20 ; Merged with always0~1 ;
; always0~22 ; Merged with always0~1 ;
; always0~24 ; Merged with always0~1 ;
; always0~26 ; Merged with always0~1 ;
; always0~28 ; Merged with always0~1 ;
; always0~30 ; Merged with always0~1 ;
; always0~32 ; Merged with always0~1 ;
; tmp_data[0] ; Merged with tmp_addr[0] ;
; tmp_data[1] ; Merged with tmp_addr[1] ;
; tmp_data[2] ; Merged with tmp_addr[2] ;
; tmp_data[3] ; Merged with tmp_addr[3] ;
; tmp_data[4] ; Merged with tmp_addr[4] ;
; tmp_data[5] ; Merged with tmp_addr[5] ;
; tmp_data[6] ; Merged with tmp_addr[6] ;
; tmp_data[7] ; Merged with tmp_addr[7] ;
; tmp_data[8] ; Merged with tmp_addr[8] ;
; tmp_data[9] ; Merged with tmp_addr[9] ;
; tmp_data[10] ; Merged with tmp_addr[10] ;
; tmp_data[11] ; Merged with tmp_addr[11] ;
; tmp_data[12] ; Merged with tmp_addr[12] ;
; tmp_data[13] ; Merged with tmp_addr[13] ;
; tmp_data[14] ; Merged with tmp_addr[14] ;
; tmp_data[15] ; Merged with tmp_addr[15] ;
; Total Number of Removed Registers = 31 ; ;
+----------------------------------------+--------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 82 ;
; Number of registers using Synchronous Clear ; 18 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 63 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1 ; 18 bits ; 36 LEs ; 18 LEs ; 18 LEs ; Yes ; |SRAM_2|SRAM_ADDR[0]~reg0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: CLK_10MHZ:M1|altpll:altpll_component ;
+-------------------------------+-------------------+-------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------------+-------------------+-------------------------------+
; OPERATION_MODE ; NORMAL ; Untyped ;
; PLL_TYPE ; FAST ; Untyped ;
; QUALIFY_CONF_DONE ; OFF ; Untyped ;
; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
; SCAN_CHAIN ; LONG ; Untyped ;
; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ;
; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
; GATE_LOCK_SIGNAL ; NO ; Untyped ;
; GATE_LOCK_COUNTER ; 0 ; Untyped ;
; LOCK_HIGH ; 1 ; Untyped ;
; LOCK_LOW ; 1 ; Untyped ;
; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
; SKIP_VCO ; OFF ; Untyped ;
; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
; BANDWIDTH ; 0 ; Untyped ;
; BANDWIDTH_TYPE ; AUTO ; Untyped ;
; SPREAD_FREQUENCY ; 0 ; Untyped ;
; DOWN_SPREAD ; 0 ; Untyped ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
; CLK1_MULTIPLY_BY ; 1 ; Untyped ;
; CLK0_MULTIPLY_BY ; 1 ; Signed Integer ;
; CLK9_DIVIDE_BY ; 0 ; Untyped ;
; CLK8_DIVIDE_BY ; 0 ; Untyped ;
; CLK7_DIVIDE_BY ; 0 ; Untyped ;
; CLK6_DIVIDE_BY ; 0 ; Untyped ;
; CLK5_DIVIDE_BY ; 1 ; Untyped ;
; CLK4_DIVIDE_BY ; 1 ; Untyped ;
; CLK3_DIVIDE_BY ; 1 ; Untyped ;
; CLK2_DIVIDE_BY ; 1 ; Untyped ;
; CLK1_DIVIDE_BY ; 1 ; Untyped ;
; CLK0_DIVIDE_BY ; 5 ; Signed Integer ;
; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_TIME_DELAY ; 0 ; Untyped ;
; CLK4_TIME_DELAY ; 0 ; Untyped ;
; CLK3_TIME_DELAY ; 0 ; Untyped ;
; CLK2_TIME_DELAY ; 0 ; Untyped ;
; CLK1_TIME_DELAY ; 0 ; Untyped ;
; CLK0_TIME_DELAY ; 0 ; Untyped ;
; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
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