sram_2.fit.rpt

FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序

+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                          ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                 ; Setting                        ; Default Value                  ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                 ; EP2C35F672C6                   ;                                ;
; Fit Attempts to Skip                                   ; 0                              ; 0.0                            ;
; Always Enable Input Buffers                            ; Off                            ; Off                            ;
; Router Timing Optimization Level                       ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                            ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                               ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                   ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                            ; Off                            ; Off                            ;
; PowerPlay Power Optimization                           ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                        ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing             ; On                             ; On                             ;
; Limit to One Fitting Attempt                           ; Off                            ; Off                            ;
; Final Placement Optimizations                          ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations            ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                          ; 1                              ; 1                              ;
; PCI I/O                                                ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                  ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                              ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                     ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/III/Cyclone II/III ; Auto                           ; Auto                           ;
; Auto Delay Chains                                      ; On                             ; On                             ;
; Auto Merge PLLs                                        ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                      ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic     ; Off                            ; Off                            ;
; Perform Register Duplication                           ; Off                            ; Off                            ;
; Perform Register Retiming                              ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                 ; Off                            ; Off                            ;
; Fitter Effort                                          ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                        ; Normal                         ; Normal                         ;
; Auto Global Clock                                      ; On                             ; On                             ;
; Auto Global Register Control Signals                   ; On                             ; On                             ;
; Stop After Congestion Map Generation                   ; Off                            ; Off                            ;
; Use smart compilation                                  ; Off                            ; Off                            ;
+--------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Administrator/桌面/SRAM_2/SRAM_2.pin.


+--------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                    ;
+---------------------------------------------+----------------------------------------------------+
; Resource                                    ; Usage                                              ;
+---------------------------------------------+----------------------------------------------------+
; Total logic elements                        ; 90 / 33,216 ( < 1 % )                              ;
;     -- Combinational with no register       ; 8                                                  ;
;     -- Register only                        ; 17                                                 ;
;     -- Combinational with a register        ; 65                                                 ;
;                                             ;                                                    ;
; Logic element usage by number of LUT inputs ;                                                    ;
;     -- 4 input functions                    ; 34                                                 ;
;     -- 3 input functions                    ; 20                                                 ;
;     -- <=2 input functions                  ; 19                                                 ;
;     -- Register only                        ; 17                                                 ;
;                                             ;                                                    ;
; Logic elements by mode                      ;                                                    ;
;     -- normal mode                          ; 56                                                 ;
;     -- arithmetic mode                      ; 17                                                 ;
;                                             ;                                                    ;
; Total registers*                            ; 82 / 34,593 ( < 1 % )                              ;
;     -- Dedicated logic registers            ; 82 / 33,216 ( < 1 % )                              ;
;     -- I/O registers                        ; 0 / 1,377 ( 0 % )                                  ;
;                                             ;                                                    ;
; Total LABs:  partially or completely used   ; 7 / 2,076 ( < 1 % )                                ;
; User inserted logic elements                ; 0                                                  ;
; Virtual pins                                ; 0                                                  ;
; I/O pins                                    ; 117 / 475 ( 25 % )                                 ;
;     -- Clock pins                           ; 8 / 8 ( 100 % )                                    ;
; Global signals                              ; 1                                                  ;
; M4Ks                                        ; 0 / 105 ( 0 % )                                    ;