sram_2.fit.rpt

FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序

Fitter report for SRAM_2
Fri Jun 08 21:48:35 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. Bidir Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. PLL Summary
 12. PLL Usage
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Delay Chain Summary
 16. Pad To Core Delay Chain Fanout
 17. Control Signals
 18. Global & Other Fast Signals
 19. Non-Global High Fan-Out Signals
 20. Interconnect Usage Summary
 21. LAB Logic Elements
 22. LAB-wide Signals
 23. LAB Signals Sourced
 24. LAB Signals Sourced Out
 25. LAB Distinct Inputs
 26. Fitter Device Options
 27. Advanced Data - General
 28. Advanced Data - Placement Preparation
 29. Advanced Data - Placement
 30. Advanced Data - Routing
 31. Fitter Messages
 32. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Fitter Summary                                                               ;
+------------------------------------+-----------------------------------------+
; Fitter Status                      ; Successful - Fri Jun 08 21:48:35 2007   ;
; Quartus II Version                 ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name                      ; SRAM_2                                  ;
; Top-level Entity Name              ; SRAM_2                                  ;
; Family                             ; Cyclone II                              ;
; Device                             ; EP2C35F672C6                            ;
; Timing Models                      ; Final                                   ;
; Total logic elements               ; 90 / 33,216 ( < 1 % )                   ;
;     Total combinational functions  ; 73 / 33,216 ( < 1 % )                   ;
;     Dedicated logic registers      ; 82 / 33,216 ( < 1 % )                   ;
; Total registers                    ; 82                                      ;
; Total pins                         ; 117 / 475 ( 25 % )                      ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 0 / 483,840 ( 0 % )                     ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                          ;
; Total PLLs                         ; 1 / 4 ( 25 % )                          ;