sram_2.tan.summary

FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.876 ns
From           : KEY[0]
To             : tmp_addr[17]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.347 ns
From           : HEX3[6]~reg0
To             : HEX3[6]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.411 ns
From           : KEY[0]
To             : SRAM_WE_N
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.019 ns
From           : SW[5]
To             : SRAM_ADDR[5]~reg0
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0'
Slack          : 94.368 ns
Required Time  : 10.00 MHz ( period = 100.000 ns )
Actual Time    : 177.56 MHz ( period = 5.632 ns )
From           : tmp_addr[15]
To             : tmp_addr[17]
From Clock     : CLK_10MHZ:M1|altpll:altpll_component|_clk0
To Clock       : CLK_10MHZ:M1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0'
Slack          : 0.555 ns
Required Time  : 10.00 MHz ( period = 100.000 ns )
Actual Time    : N/A
From           : tmp_addr[7]
To             : SRAM_DQ[7]~reg0
From Clock     : CLK_10MHZ:M1|altpll:altpll_component|_clk0
To Clock       : CLK_10MHZ:M1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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