sram_2.map.smsg

FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jun 08 21:47:22 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SRAM_2 -c SRAM_2
Info: Found 1 design units, including 1 entities, in source file CLK_10MHZ.v
    Info: Found entity 1: CLK_10MHZ
Info: Found 1 design units, including 1 entities, in source file SRAM_2.v
    Info: Found entity 1: SRAM_2
Info: Elaborating entity "SRAM_2" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at SRAM_2.v(44): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at SRAM_2.v(47): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at SRAM_2.v(67): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SRAM_2.v(68): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at SRAM_2.v(79): truncated value with size 32 to match size of target (16)
Warning (10034): Output port "LEDG[8]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[7]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[6]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[5]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[4]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[3]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[2]" at SRAM_2.v(28) has no driver
Warning (10034): Output port "LEDG[1]" at SRAM_2.v(28) has no driver
Info: Elaborating entity "CLK_10MHZ" for hierarchy "CLK_10MHZ:M1"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/70/quartus/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "CLK_10MHZ:M1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "CLK_10MHZ:M1|altpll:altpll_component"
Info: Duplicate registers merged to single register
    Info: Duplicate register "always0~4" merged to single register "always0~1"
    Info: Duplicate register "always0~6" merged to single register "always0~1"
    Info: Duplicate register "always0~8" merged to single register "always0~1"
    Info: Duplicate register "always0~10" merged to single register "always0~1"
    Info: Duplicate register "always0~12" merged to single register "always0~1"
    Info: Duplicate register "always0~14" merged to single register "always0~1"
    Info: Duplicate register "always0~16" merged to single register "always0~1"
    Info: Duplicate register "always0~18" merged to single register "always0~1"
    Info: Duplicate register "always0~20" merged to single register "always0~1"
    Info: Duplicate register "always0~22" merged to single register "always0~1"
    Info: Duplicate register "always0~24" merged to single register "always0~1"
    Info: Duplicate register "always0~26" merged to single register "always0~1"
    Info: Duplicate register "always0~28" merged to single register "always0~1"
    Info: Duplicate register "always0~30" merged to single register "always0~1"
    Info: Duplicate register "always0~32" merged to single register "always0~1"
Info: Duplicate registers merged to single register
    Info: Duplicate register "tmp_data[0]" merged to single register "tmp_addr[0]"
    Info: Duplicate register "tmp_data[1]" merged to single register "tmp_addr[1]"
    Info: Duplicate register "tmp_data[2]" merged to single register "tmp_addr[2]"
    Info: Duplicate register "tmp_data[3]" merged to single register "tmp_addr[3]"
    Info: Duplicate register "tmp_data[4]" merged to single register "tmp_addr[4]"
    Info: Duplicate register "tmp_data[5]" merged to single register "tmp_addr[5]"
    Info: Duplicate register "tmp_data[6]" merged to single register "tmp_addr[6]"
    Info: Duplicate register "tmp_data[7]" merged to single register "tmp_addr[7]"
    Info: Duplicate register "tmp_data[8]" merged to single register "tmp_addr[8]"
    Info: Duplicate register "tmp_data[9]" merged to single register "tmp_addr[9]"
    Info: Duplicate register "tmp_data[10]" merged to single register "tmp_addr[10]"
    Info: Duplicate register "tmp_data[11]" merged to single register "tmp_addr[11]"
    Info: Duplicate register "tmp_data[12]" merged to single register "tmp_addr[12]"
    Info: Duplicate register "tmp_data[13]" merged to single register "tmp_addr[13]"
    Info: Duplicate register "tmp_data[14]" merged to single register "tmp_addr[14]"
    Info: Duplicate register "tmp_data[15]" merged to single register "tmp_addr[15]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "LEDG[1]" stuck at GND
    Warning: Pin "LEDG[2]" stuck at GND
    Warning: Pin "LEDG[3]" stuck at GND
    Warning: Pin "LEDG[4]" stuck at GND
    Warning: Pin "LEDG[5]" stuck at GND
    Warning: Pin "LEDG[6]" stuck at GND
    Warning: Pin "LEDG[7]" stuck at GND
    Warning: Pin "LEDG[8]" stuck at GND
    Warning: Pin "SRAM_CE_N" stuck at GND
    Warning: Pin "SRAM_UB_N" stuck at GND
    Warning: Pin "SRAM_LB_N" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "KEY[1]"
Info: Implemented 208 device resources after synthesis - the final resource count might be different
    Info: Implemented 23 input pins
    Info: Implemented 78 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 90 logic cells
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 27 warnings
    Info: Allocated 130 megabytes of memory during processing
    Info: Processing ended: Fri Jun 08 21:47:32 2007
    Info: Elapsed time: 00:00:10