sram_2.v

FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序

module SRAM_2(
	//output 
	HEX0,
	HEX1,
	HEX2,
	HEX3,
	
	LEDG,
	LEDR, //indicate which SW is changed	
	
	//input
	SW,
	KEY,
	CLOCK_50,	
	//inout
	SRAM_DQ,
	//output
	SRAM_ADDR,
	SRAM_CE_N,
	SRAM_OE_N,
	SRAM_WE_N,
	SRAM_UB_N,
	SRAM_LB_N				
	);

output [6:0] HEX0, HEX1, HEX2, HEX3;
reg [6:0] HEX0, HEX1, HEX2, HEX3;
output [8:0] LEDG;
reg [8:0] LEDG;
output [17:0] LEDR;

input [17:0] SW;
input [3:0] KEY;
input CLOCK_50;

//SRAM
inout [15:0] SRAM_DQ;
reg [15:0] SRAM_DQ;
output SRAM_CE_N, SRAM_OE_N, SRAM_WE_N, SRAM_UB_N, SRAM_LB_N;
output [17:0] SRAM_ADDR;
reg [17:0] SRAM_ADDR;

assign SRAM_CE_N = 0;
assign SRAM_OE_N = (KEY[2] == 0)?0:1; //when KEY[2] is pressed, we can read from sram
assign SRAM_UB_N = 0;
assign SRAM_LB_N = 0;
assign SRAM_WE_N = (KEY[0] == 0)?0:1;
assign LEDR = SW;

reg [15:0] tmp_data;
reg [17:0] tmp_addr;

wire clk;
CLK_10MHZ M1(
	CLOCK_50,
	clk);

always @(posedge clk) begin:cyclone
	if(KEY[3] == 0) begin
		tmp_addr <= 0;
		tmp_data <= 0;
	end
	else if((KEY[0] == 0) && (tmp_addr < 262001)) begin
		SRAM_DQ <= tmp_data; //数据口赋值后一定要在后面设置为高阻，不然就会锁存，即保留
							 //最后一次所赋的值
		SRAM_ADDR <= tmp_addr;
		tmp_data <= tmp_data + 1;
		tmp_addr <= tmp_addr + 1;
	end 
	else begin//居然成功了！！！
//		SRAM_DQ <= 'bz;  //here set data prot to High Z
//		SRAM_ADDR <= 'bz;
				
	end

	
	if(KEY[2] == 0) begin

		SRAM_DQ <= 'bz;  //OR here set data prot to High Z
		SRAM_ADDR <= SW;
		HEX0 <= set_HEX({1'b0,SRAM_DQ[3:0]});
		HEX1 <= set_HEX({1'b0,SRAM_DQ[7:4]});
		HEX2 <= set_HEX({1'b0,SRAM_DQ[11:8]});
		HEX3 <= set_HEX({1'b0,SRAM_DQ[15:12]});
	end	
	
end

always @(posedge clk) begin
	if(KEY[3] == 0)
		LEDG[0] = 0;
	else if(tmp_addr >= 262001)
		LEDG[0] = 1;
	else
		LEDG[0] = 0;	
end




//table of HEX
function [6:0] set_HEX;
	input [4:0] num;
	begin
    	case(num)
			5'b00000: set_HEX = 7'b100_0000; //0
			5'b00001: set_HEX = 7'b111_1001; //1
			5'b00010: set_HEX = 7'b010_0100; //2
			5'b00011: set_HEX = 7'b011_0000; //3
			5'b00100: set_HEX = 7'b001_1001; //4
			5'b00101: set_HEX = 7'b001_0010; //5
			5'b00110: set_HEX = 7'b000_0010; //6
			5'b00111: set_HEX = 7'b111_1000; //7
			5'b01000: set_HEX = 7'b000_0000; //8
			5'b01001: set_HEX = 7'b001_1000; //9
			5'b01010: set_HEX = 7'b000_1000; //A
			5'b01011: set_HEX = 7'b000_0011; //B
			5'b01100: set_HEX = 7'b100_0110; //C
			5'b01101: set_HEX = 7'b010_0001; //D
			5'b01110: set_HEX = 7'b000_0110; //E
			5'b01111: set_HEX = 7'b000_1110; //F
			default: set_HEX = 7'b111_1111; //default
		endcase
    end
endfunction


endmodule