sram_2.tan.rpt

FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                             ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                            ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 10.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 1                     ; 5                   ; -2.358 ns ;              ;
; CLOCK_50                                   ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK_10MHZ:M1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+--------------+--------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From         ; To           ; From Clock                                 ; To Clock                                   ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------+--------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 94.368 ns                               ; 177.56 MHz ( period = 5.632 ns )                    ; tmp_addr[15] ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.786 ns                 ; 5.418 ns                ;
; 94.389 ns                               ; 178.22 MHz ( period = 5.611 ns )                    ; tmp_addr[3]  ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.398 ns                ;
; 94.425 ns                               ; 179.37 MHz ( period = 5.575 ns )                    ; tmp_addr[2]  ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.362 ns                ;
; 94.502 ns                               ; 181.88 MHz ( period = 5.498 ns )                    ; tmp_addr[5]  ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.285 ns                ;
; 94.522 ns                               ; 182.55 MHz ( period = 5.478 ns )                    ; tmp_addr[14] ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.786 ns                 ; 5.264 ns                ;
; 94.527 ns                               ; 182.72 MHz ( period = 5.473 ns )                    ; tmp_addr[15] ; tmp_addr[16] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.786 ns                 ; 5.259 ns                ;
; 94.543 ns                               ; 183.25 MHz ( period = 5.457 ns )                    ; tmp_addr[0]  ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.244 ns                ;
; 94.548 ns                               ; 183.42 MHz ( period = 5.452 ns )                    ; tmp_addr[3]  ; tmp_addr[16] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.239 ns                ;
; 94.584 ns                               ; 184.64 MHz ( period = 5.416 ns )                    ; tmp_addr[2]  ; tmp_addr[16] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.203 ns                ;
; 94.592 ns                               ; 184.91 MHz ( period = 5.408 ns )                    ; tmp_addr[8]  ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.195 ns                ;
; 94.596 ns                               ; 185.05 MHz ( period = 5.404 ns )                    ; tmp_addr[1]  ; tmp_addr[17] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.191 ns                ;
; 94.598 ns                               ; 185.12 MHz ( period = 5.402 ns )                    ; tmp_addr[15] ; tmp_addr[15] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.786 ns                 ; 5.188 ns                ;
; 94.619 ns                               ; 185.84 MHz ( period = 5.381 ns )                    ; tmp_addr[3]  ; tmp_addr[15] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.168 ns                ;
; 94.655 ns                               ; 187.09 MHz ( period = 5.345 ns )                    ; tmp_addr[2]  ; tmp_addr[15] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.132 ns                ;
; 94.661 ns                               ; 187.30 MHz ( period = 5.339 ns )                    ; tmp_addr[5]  ; tmp_addr[16] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.787 ns                 ; 5.126 ns                ;
; 94.669 ns                               ; 187.58 MHz ( period = 5.331 ns )                    ; tmp_addr[15] ; tmp_addr[14] ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; CLK_10MHZ:M1|altpll:altpll_component|_clk0 ; 100.000 ns                  ; 99.786 ns                 ; 5.117 ns                ;