sram_2.fit.eqn

FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序

LEDG[5] = OUTPUT(GND);


--LEDG[6] is LEDG[6] at PIN_AA20
--operation mode is output

LEDG[6] = OUTPUT(GND);


--LEDG[7] is LEDG[7] at PIN_Y18
--operation mode is output

LEDG[7] = OUTPUT(GND);


--LEDG[8] is LEDG[8] at PIN_Y12
--operation mode is output

LEDG[8] = OUTPUT(GND);


--LEDR[0] is LEDR[0] at PIN_AE23
--operation mode is output

LEDR[0] = OUTPUT(SW[0]);


--LEDR[1] is LEDR[1] at PIN_AF23
--operation mode is output

LEDR[1] = OUTPUT(SW[1]);


--LEDR[2] is LEDR[2] at PIN_AB21
--operation mode is output

LEDR[2] = OUTPUT(SW[2]);


--LEDR[3] is LEDR[3] at PIN_AC22
--operation mode is output

LEDR[3] = OUTPUT(SW[3]);


--LEDR[4] is LEDR[4] at PIN_AD22
--operation mode is output

LEDR[4] = OUTPUT(SW[4]);


--LEDR[5] is LEDR[5] at PIN_AD23
--operation mode is output

LEDR[5] = OUTPUT(SW[5]);


--LEDR[6] is LEDR[6] at PIN_AD21
--operation mode is output

LEDR[6] = OUTPUT(SW[6]);


--LEDR[7] is LEDR[7] at PIN_AC21
--operation mode is output

LEDR[7] = OUTPUT(SW[7]);


--LEDR[8] is LEDR[8] at PIN_AA14
--operation mode is output

LEDR[8] = OUTPUT(SW[8]);


--LEDR[9] is LEDR[9] at PIN_Y13
--operation mode is output

LEDR[9] = OUTPUT(SW[9]);


--LEDR[10] is LEDR[10] at PIN_AA13
--operation mode is output

LEDR[10] = OUTPUT(SW[10]);


--LEDR[11] is LEDR[11] at PIN_AC14
--operation mode is output

LEDR[11] = OUTPUT(SW[11]);


--LEDR[12] is LEDR[12] at PIN_AD15
--operation mode is output

LEDR[12] = OUTPUT(SW[12]);


--LEDR[13] is LEDR[13] at PIN_AE15
--operation mode is output

LEDR[13] = OUTPUT(SW[13]);


--LEDR[14] is LEDR[14] at PIN_AF13
--operation mode is output

LEDR[14] = OUTPUT(SW[14]);


--LEDR[15] is LEDR[15] at PIN_AE13
--operation mode is output

LEDR[15] = OUTPUT(SW[15]);


--LEDR[16] is LEDR[16] at PIN_AE12
--operation mode is output

LEDR[16] = OUTPUT(SW[16]);


--LEDR[17] is LEDR[17] at PIN_AD12
--operation mode is output

LEDR[17] = OUTPUT(SW[17]);


--SRAM_ADDR[0] is SRAM_ADDR[0] at PIN_AE4
--operation mode is output

SRAM_ADDR[0] = OUTPUT(A1L107Q);


--SRAM_ADDR[1] is SRAM_ADDR[1] at PIN_AF4
--operation mode is output

SRAM_ADDR[1] = OUTPUT(A1L109Q);


--SRAM_ADDR[2] is SRAM_ADDR[2] at PIN_AC5
--operation mode is output

SRAM_ADDR[2] = OUTPUT(A1L111Q);


--SRAM_ADDR[3] is SRAM_ADDR[3] at PIN_AC6
--operation mode is output

SRAM_ADDR[3] = OUTPUT(A1L113Q);


--SRAM_ADDR[4] is SRAM_ADDR[4] at PIN_AD4
--operation mode is output

SRAM_ADDR[4] = OUTPUT(A1L115Q);


--SRAM_ADDR[5] is SRAM_ADDR[5] at PIN_AD5
--operation mode is output

SRAM_ADDR[5] = OUTPUT(A1L117Q);


--SRAM_ADDR[6] is SRAM_ADDR[6] at PIN_AE5
--operation mode is output

SRAM_ADDR[6] = OUTPUT(A1L119Q);


--SRAM_ADDR[7] is SRAM_ADDR[7] at PIN_AF5
--operation mode is output

SRAM_ADDR[7] = OUTPUT(A1L121Q);


--SRAM_ADDR[8] is SRAM_ADDR[8] at PIN_AD6
--operation mode is output

SRAM_ADDR[8] = OUTPUT(A1L123Q);


--SRAM_ADDR[9] is SRAM_ADDR[9] at PIN_AD7
--operation mode is output

SRAM_ADDR[9] = OUTPUT(A1L125Q);


--SRAM_ADDR[10] is SRAM_ADDR[10] at PIN_V10
--operation mode is output

SRAM_ADDR[10] = OUTPUT(A1L127Q);


--SRAM_ADDR[11] is SRAM_ADDR[11] at PIN_V9
--operation mode is output

SRAM_ADDR[11] = OUTPUT(A1L129Q);


--SRAM_ADDR[12] is SRAM_ADDR[12] at PIN_AC7
--operation mode is output

SRAM_ADDR[12] = OUTPUT(A1L131Q);


--SRAM_ADDR[13] is SRAM_ADDR[13] at PIN_W8
--operation mode is output

SRAM_ADDR[13] = OUTPUT(A1L133Q);


--SRAM_ADDR[14] is SRAM_ADDR[14] at PIN_W10
--operation mode is output

SRAM_ADDR[14] = OUTPUT(A1L135Q);


--SRAM_ADDR[15] is SRAM_ADDR[15] at PIN_Y10
--operation mode is output

SRAM_ADDR[15] = OUTPUT(A1L137Q);


--SRAM_ADDR[16] is SRAM_ADDR[16] at PIN_AB8
--operation mode is output

SRAM_ADDR[16] = OUTPUT(A1L139Q);


--SRAM_ADDR[17] is SRAM_ADDR[17] at PIN_AC8
--operation mode is output

SRAM_ADDR[17] = OUTPUT(A1L141Q);


--SRAM_CE_N is SRAM_CE_N at PIN_AC11
--operation mode is output

SRAM_CE_N = OUTPUT(GND);


--SRAM_OE_N is SRAM_OE_N at PIN_AD10
--operation mode is output

SRAM_OE_N = OUTPUT(KEY[2]);


--SRAM_WE_N is SRAM_WE_N at PIN_AE10
--operation mode is output

SRAM_WE_N = OUTPUT(KEY[0]);


--SRAM_UB_N is SRAM_UB_N at PIN_AF9
--operation mode is output

SRAM_UB_N = OUTPUT(GND);


--SRAM_LB_N is SRAM_LB_N at PIN_AE9
--operation mode is output

SRAM_LB_N = OUTPUT(GND);


--A1L163 is SRAM_DQ[0]~15 at PIN_AD8
--operation mode is bidir

A1L163 = SRAM_DQ[0];

--SRAM_DQ[0] is SRAM_DQ[0] at PIN_AD8
--operation mode is bidir

SRAM_DQ[0]_tri_out = TRI(A1L164Q, A1L243Q);
SRAM_DQ[0] = BIDIR(SRAM_DQ[0]_tri_out);


--A1L166 is SRAM_DQ[1]~14 at PIN_AE6
--operation mode is bidir

A1L166 = SRAM_DQ[1];

--SRAM_DQ[1] is SRAM_DQ[1] at PIN_AE6
--operation mode is bidir

SRAM_DQ[1]_tri_out = TRI(A1L167Q, A1L243Q);
SRAM_DQ[1] = BIDIR(SRAM_DQ[1]_tri_out);


--A1L170 is SRAM_DQ[2]~13 at PIN_AF6
--operation mode is bidir

A1L170 = SRAM_DQ[2];

--SRAM_DQ[2] is SRAM_DQ[2] at PIN_AF6
--operation mode is bidir

SRAM_DQ[2]_tri_out = TRI(A1L171Q, A1L243Q);
SRAM_DQ[2] = BIDIR(SRAM_DQ[2]_tri_out);


--A1L174 is SRAM_DQ[3]~12 at PIN_AA9
--operation mode is bidir

A1L174 = SRAM_DQ[3];

--SRAM_DQ[3] is SRAM_DQ[3] at PIN_AA9
--operation mode is bidir

SRAM_DQ[3]_tri_out = TRI(A1L175Q, A1L243Q);
SRAM_DQ[3] = BIDIR(SRAM_DQ[3]_tri_out);


--A1L178 is SRAM_DQ[4]~11 at PIN_AA10
--operation mode is bidir

A1L178 = SRAM_DQ[4];

--SRAM_DQ[4] is SRAM_DQ[4] at PIN_AA10
--operation mode is bidir

SRAM_DQ[4]_tri_out = TRI(A1L179Q, A1L243Q);
SRAM_DQ[4] = BIDIR(SRAM_DQ[4]_tri_out);


--A1L181 is SRAM_DQ[5]~10 at PIN_AB10
--operation mode is bidir

A1L181 = SRAM_DQ[5];

--SRAM_DQ[5] is SRAM_DQ[5] at PIN_AB10
--operation mode is bidir

SRAM_DQ[5]_tri_out = TRI(A1L182Q, A1L243Q);
SRAM_DQ[5] = BIDIR(SRAM_DQ[5]_tri_out);


--A1L185 is SRAM_DQ[6]~9 at PIN_AA11
--operation mode is bidir

A1L185 = SRAM_DQ[6];

--SRAM_DQ[6] is SRAM_DQ[6] at PIN_AA11
--operation mode is bidir

SRAM_DQ[6]_tri_out = TRI(A1L186Q, A1L243Q);
SRAM_DQ[6] = BIDIR(SRAM_DQ[6]_tri_out);


--A1L188 is SRAM_DQ[7]~8 at PIN_Y11
--operation mode is bidir

A1L188 = SRAM_DQ[7];

--SRAM_DQ[7] is SRAM_DQ[7] at PIN_Y11
--operation mode is bidir

SRAM_DQ[7]_tri_out = TRI(A1L189Q, A1L243Q);
SRAM_DQ[7] = BIDIR(SRAM_DQ[7]_tri_out);


--A1L192 is SRAM_DQ[8]~7 at PIN_AE7
--operation mode is bidir

A1L192 = SRAM_DQ[8];

--SRAM_DQ[8] is SRAM_DQ[8] at PIN_AE7
--operation mode is bidir

SRAM_DQ[8]_tri_out = TRI(A1L193Q, A1L243Q);
SRAM_DQ[8] = BIDIR(SRAM_DQ[8]_tri_out);


--A1L196 is SRAM_DQ[9]~6 at PIN_AF7
--operation mode is bidir

A1L196 = SRAM_DQ[9];

--SRAM_DQ[9] is SRAM_DQ[9] at PIN_AF7
--operation mode is bidir

SRAM_DQ[9]_tri_out = TRI(A1L197Q, A1L243Q);
SRAM_DQ[9] = BIDIR(SRAM_DQ[9]_tri_out);


--A1L199 is SRAM_DQ[10]~5 at PIN_AE8
--operation mode is bidir

A1L199 = SRAM_DQ[10];

--SRAM_DQ[10] is SRAM_DQ[10] at PIN_AE8
--operation mode is bidir

SRAM_DQ[10]_tri_out = TRI(A1L200Q, A1L243Q);
SRAM_DQ[10] = BIDIR(SRAM_DQ[10]_tri_out);


--A1L203 is SRAM_DQ[11]~4 at PIN_AF8
--operation mode is bidir

A1L203 = SRAM_DQ[11];

--SRAM_DQ[11] is SRAM_DQ[11] at PIN_AF8
--operation mode is bidir

SRAM_DQ[11]_tri_out = TRI(A1L204Q, A1L243Q);
SRAM_DQ[11] = BIDIR(SRAM_DQ[11]_tri_out);


--A1L206 is SRAM_DQ[12]~3 at PIN_W11
--operation mode is bidir

A1L206 = SRAM_DQ[12];

--SRAM_DQ[12] is SRAM_DQ[12] at PIN_W11
--operation mode is bidir

SRAM_DQ[12]_tri_out = TRI(A1L207Q, A1L243Q);
SRAM_DQ[12] = BIDIR(SRAM_DQ[12]_tri_out);


--A1L209 is SRAM_DQ[13]~2 at PIN_W12
--operation mode is bidir

A1L209 = SRAM_DQ[13];

--SRAM_DQ[13] is SRAM_DQ[13] at PIN_W12
--operation mode is bidir

SRAM_DQ[13]_tri_out = TRI(A1L210Q, A1L243Q);
SRAM_DQ[13] = BIDIR(SRAM_DQ[13]_tri_out);


--A1L213 is SRAM_DQ[14]~1 at PIN_AC9
--operation mode is bidir

A1L213 = SRAM_DQ[14];

--SRAM_DQ[14] is SRAM_DQ[14] at PIN_AC9
--operation mode is bidir

SRAM_DQ[14]_tri_out = TRI(A1L214Q, A1L243Q);
SRAM_DQ[14] = BIDIR(SRAM_DQ[14]_tri_out);


--A1L217 is SRAM_DQ[15]~0 at PIN_AC10
--operation mode is bidir

A1L217 = SRAM_DQ[15];

--SRAM_DQ[15] is SRAM_DQ[15] at PIN_AC10
--operation mode is bidir

SRAM_DQ[15]_tri_out = TRI(A1L218Q, A1L243Q);
SRAM_DQ[15] = BIDIR(SRAM_DQ[15]_tri_out);





--C1L2 is CLK_10MHZ:M1|altpll:altpll_component|_clk0~clkctrl at CLKCTRL_G3
C1L2 = cycloneii_clkctrl(.INCLK[0] = C1__clk0) WITH (clock_type = "Global Clock");


--A1L244 is always0~0feeder at LCCOMB_X15_Y1_N8
A1L244 = KEY[2];


--A1L194 is SRAM_DQ[8]~reg0feeder at LCCOMB_X16_Y2_N12
A1L194 = tmp_addr[8];


--A1L201 is SRAM_DQ[10]~reg0feeder at LCCOMB_X17_Y1_N4
A1L201 = tmp_addr[10];


--A1L211 is SRAM_DQ[13]~reg0feeder at LCCOMB_X17_Y1_N10
A1L211 = tmp_addr[13];


--A1L215 is SRAM_DQ[14]~reg0feeder at LCCOMB_X17_Y1_N30
A1L215 = tmp_addr[14];


--A1L219 is SRAM_DQ[15]~reg0feeder at LCCOMB_X17_Y1_N6
A1L219 = tmp_addr[15];


--A1L190 is SRAM_DQ[7]~reg0feeder at LCCOMB_X16_Y2_N10
A1L190 = tmp_addr[7];


--A1L168 is SRAM_DQ[1]~reg0feeder at LCCOMB_X15_Y1_N2
A1L168 = tmp_addr[1];


--A1L172 is SRAM_DQ[2]~reg0feeder at LCCOMB_X15_Y1_N10
A1L172 = tmp_addr[2];


--A1L176 is SRAM_DQ[3]~reg0feeder at LCCOMB_X16_Y2_N4
A1L176 = tmp_addr[3];


--A1L183 is SRAM_DQ[5]~reg0feeder at LCCOMB_X15_Y1_N12
A1L183 = tmp_addr[5];