📄 io_map.h
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#define PWM_PMICCR_ICC1_MASK 2U
#define PWM_PMICCR_ICC2_MASK 4U
#define PWM_PMICCR_ICC_MASK 7U
#define PWM_PMICCR_ICC_BITNUM 0U
#define PWM_PMICCR *((volatile word *)0x0000F053)
/*** PWM_PMSRC - PWM Source Control Register; 0x0000F054 ***/
union {
word Word;
} PWM_PMSRC_STR;
#define PWM_PMSRC_SRC00_MASK 1U
#define PWM_PMSRC_SRC01_MASK 2U
#define PWM_PMSRC_SRC10_MASK 4U
#define PWM_PMSRC_SRC11_MASK 8U
#define PWM_PMSRC_SRC12_MASK 16U
#define PWM_PMSRC_SRC20_MASK 32U
#define PWM_PMSRC_SRC21_MASK 64U
#define PWM_PMSRC_SRC22_MASK 128U
#define PWM_PMSRC_CINV0_MASK 256U
#define PWM_PMSRC_CINV1_MASK 512U
#define PWM_PMSRC_CINV2_MASK 1024U
#define PWM_PMSRC_CINV3_MASK 2048U
#define PWM_PMSRC_CINV4_MASK 4096U
#define PWM_PMSRC_CINV5_MASK 8192U
#define PWM_PMSRC_SRC0_MASK 3U
#define PWM_PMSRC_SRC0_BITNUM 0U
#define PWM_PMSRC_SRC1_MASK 28U
#define PWM_PMSRC_SRC1_BITNUM 2U
#define PWM_PMSRC_SRC2_MASK 224U
#define PWM_PMSRC_SRC2_BITNUM 5U
#define PWM_PMSRC_CINV_MASK 16128U
#define PWM_PMSRC_CINV_BITNUM 8U
#define PWM_PMSRC *((volatile word *)0x0000F054)
word Reserved0[11]; /* Reserved (unused) registers */
} PWM_PRPH;
/******************************************
*** Peripheral INTC
*******************************************/
typedef volatile struct {
/*** INTC_IPR0 - Interrupt Priority Register 0; 0x0000F060 ***/
union {
word Word;
} INTC_IPR0_STR;
#define INTC_IPR0_STPCNT_IPL0_MASK 1U
#define INTC_IPR0_STPCNT_IPL1_MASK 2U
#define INTC_IPR0_BKPT_U0_IPL0_MASK 4U
#define INTC_IPR0_BKPT_U0_IPL1_MASK 8U
#define INTC_IPR0_TRBUF_IPL0_MASK 16U
#define INTC_IPR0_TRBUF_IPL1_MASK 32U
#define INTC_IPR0_TX_REG_IPL0_MASK 64U
#define INTC_IPR0_TX_REG_IPL1_MASK 128U
#define INTC_IPR0_RX_REG_IPL0_MASK 256U
#define INTC_IPR0_RX_REG_IPL1_MASK 512U
#define INTC_IPR0_LVI_IPL0_MASK 16384U
#define INTC_IPR0_LVI_IPL1_MASK 32768U
#define INTC_IPR0_STPCNT_IPL_MASK 3U
#define INTC_IPR0_STPCNT_IPL_BITNUM 0U
#define INTC_IPR0_BKPT_U0_IPL_MASK 12U
#define INTC_IPR0_BKPT_U0_IPL_BITNUM 2U
#define INTC_IPR0_TRBUF_IPL_MASK 48U
#define INTC_IPR0_TRBUF_IPL_BITNUM 4U
#define INTC_IPR0_TX_REG_IPL_MASK 192U
#define INTC_IPR0_TX_REG_IPL_BITNUM 6U
#define INTC_IPR0_RX_REG_IPL_MASK 768U
#define INTC_IPR0_RX_REG_IPL_BITNUM 8U
#define INTC_IPR0_LVI_IPL_MASK 49152U
#define INTC_IPR0_LVI_IPL_BITNUM 14U
#define INTC_IPR0 *((volatile word *)0x0000F060)
/*** INTC_IPR1 - Interrupt Priority Register 1; 0x0000F061 ***/
union {
word Word;
} INTC_IPR1_STR;
#define INTC_IPR1_PLL_IPL0_MASK 1U
#define INTC_IPR1_PLL_IPL1_MASK 2U
#define INTC_IPR1_HFM_ERR_IPL0_MASK 4U
#define INTC_IPR1_HFM_ERR_IPL1_MASK 8U
#define INTC_IPR1_HFM_CC_IPL0_MASK 16U
#define INTC_IPR1_HFM_CC_IPL1_MASK 32U
#define INTC_IPR1_HFM_CBE_IPL0_MASK 64U
#define INTC_IPR1_HFM_CBE_IPL1_MASK 128U
#define INTC_IPR1_GPIO_D_IPL0_MASK 1024U
#define INTC_IPR1_GPIO_D_IPL1_MASK 2048U
#define INTC_IPR1_GPIO_C_IPL0_MASK 4096U
#define INTC_IPR1_GPIO_C_IPL1_MASK 8192U
#define INTC_IPR1_GPIO_B_IPL0_MASK 16384U
#define INTC_IPR1_GPIO_B_IPL1_MASK 32768U
#define INTC_IPR1_PLL_IPL_MASK 3U
#define INTC_IPR1_PLL_IPL_BITNUM 0U
#define INTC_IPR1_HFM_ERR_IPL_MASK 12U
#define INTC_IPR1_HFM_ERR_IPL_BITNUM 2U
#define INTC_IPR1_HFM_CC_IPL_MASK 48U
#define INTC_IPR1_HFM_CC_IPL_BITNUM 4U
#define INTC_IPR1_HFM_CBE_IPL_MASK 192U
#define INTC_IPR1_HFM_CBE_IPL_BITNUM 6U
#define INTC_IPR1_GPIO_D_IPL_MASK 3072U
#define INTC_IPR1_GPIO_D_IPL_BITNUM 10U
#define INTC_IPR1_GPIO_C_IPL_MASK 12288U
#define INTC_IPR1_GPIO_C_IPL_BITNUM 12U
#define INTC_IPR1_GPIO_B_IPL_MASK 49152U
#define INTC_IPR1_GPIO_B_IPL_BITNUM 14U
#define INTC_IPR1 *((volatile word *)0x0000F061)
/*** INTC_IPR2 - Interrupt Priority Register 2; 0x0000F062 ***/
union {
word Word;
} INTC_IPR2_STR;
#define INTC_IPR2_GPIO_A_IPL0_MASK 1U
#define INTC_IPR2_GPIO_A_IPL1_MASK 2U
#define INTC_IPR2_SPI_RCV_IPL0_MASK 4U
#define INTC_IPR2_SPI_RCV_IPL1_MASK 8U
#define INTC_IPR2_SPI_XMIT_IPL0_MASK 16U
#define INTC_IPR2_SPI_XMIT_IPL1_MASK 32U
#define INTC_IPR2_SCI_XMIT_IPL0_MASK 64U
#define INTC_IPR2_SCI_XMIT_IPL1_MASK 128U
#define INTC_IPR2_SCI_TIDL_IPL0_MASK 256U
#define INTC_IPR2_SCI_TIDL_IPL1_MASK 512U
#define INTC_IPR2_SCI_RERR_IPL0_MASK 4096U
#define INTC_IPR2_SCI_RERR_IPL1_MASK 8192U
#define INTC_IPR2_SCI_RCV_IPL0_MASK 16384U
#define INTC_IPR2_SCI_RCV_IPL1_MASK 32768U
#define INTC_IPR2_GPIO_A_IPL_MASK 3U
#define INTC_IPR2_GPIO_A_IPL_BITNUM 0U
#define INTC_IPR2_SPI_RCV_IPL_MASK 12U
#define INTC_IPR2_SPI_RCV_IPL_BITNUM 2U
#define INTC_IPR2_SPI_XMIT_IPL_MASK 48U
#define INTC_IPR2_SPI_XMIT_IPL_BITNUM 4U
#define INTC_IPR2_SCI_XMIT_IPL_MASK 192U
#define INTC_IPR2_SCI_XMIT_IPL_BITNUM 6U
#define INTC_IPR2_SCI_TIDL_IPL_MASK 768U
#define INTC_IPR2_SCI_TIDL_IPL_BITNUM 8U
#define INTC_IPR2_SCI_RERR_IPL_MASK 12288U
#define INTC_IPR2_SCI_RERR_IPL_BITNUM 12U
#define INTC_IPR2_SCI_RCV_IPL_MASK 49152U
#define INTC_IPR2_SCI_RCV_IPL_BITNUM 14U
#define INTC_IPR2 *((volatile word *)0x0000F062)
/*** INTC_IPR3 - Interrupt Priority Register 3; 0x0000F063 ***/
union {
word Word;
} INTC_IPR3_STR;
#define INTC_IPR3_I2C_ADDR_IPL0_MASK 16U
#define INTC_IPR3_I2C_ADDR_IPL1_MASK 32U
#define INTC_IPR3_TMR_0_IPL0_MASK 64U
#define INTC_IPR3_TMR_0_IPL1_MASK 128U
#define INTC_IPR3_TMR_1_IPL0_MASK 256U
#define INTC_IPR3_TMR_1_IPL1_MASK 512U
#define INTC_IPR3_TMR_2_IPL0_MASK 1024U
#define INTC_IPR3_TMR_2_IPL1_MASK 2048U
#define INTC_IPR3_TMR_3_IPL0_MASK 4096U
#define INTC_IPR3_TMR_3_IPL1_MASK 8192U
#define INTC_IPR3_ADCA_CC_IPL0_MASK 16384U
#define INTC_IPR3_ADCA_CC_IPL1_MASK 32768U
#define INTC_IPR3_I2C_ADDR_IPL_MASK 48U
#define INTC_IPR3_I2C_ADDR_IPL_BITNUM 4U
#define INTC_IPR3_TMR_0_IPL_MASK 192U
#define INTC_IPR3_TMR_0_IPL_BITNUM 6U
#define INTC_IPR3_TMR_1_IPL_MASK 768U
#define INTC_IPR3_TMR_1_IPL_BITNUM 8U
#define INTC_IPR3_TMR_2_IPL_MASK 3072U
#define INTC_IPR3_TMR_2_IPL_BITNUM 10U
#define INTC_IPR3_TMR_3_IPL_MASK 12288U
#define INTC_IPR3_TMR_3_IPL_BITNUM 12U
#define INTC_IPR3_ADCA_CC_IPL_MASK 49152U
#define INTC_IPR3_ADCA_CC_IPL_BITNUM 14U
#define INTC_IPR3 *((volatile word *)0x0000F063)
/*** INTC_IPR4 - Interrupt Priority Register 4; 0x0000F064 ***/
union {
word Word;
} INTC_IPR4_STR;
#define INTC_IPR4_ADCB_CC_IPL0_MASK 1U
#define INTC_IPR4_ADCB_CC_IPL1_MASK 2U
#define INTC_IPR4_ADC_ZC_IPL0_MASK 4U
#define INTC_IPR4_ADC_ZC_IPL1_MASK 8U
#define INTC_IPR4_PWM_RL_IPL0_MASK 16U
#define INTC_IPR4_PWM_RL_IPL1_MASK 32U
#define INTC_IPR4_PWM_F_IPL0_MASK 64U
#define INTC_IPR4_PWM_F_IPL1_MASK 128U
#define INTC_IPR4_ADCB_CC_IPL_MASK 3U
#define INTC_IPR4_ADCB_CC_IPL_BITNUM 0U
#define INTC_IPR4_ADC_ZC_IPL_MASK 12U
#define INTC_IPR4_ADC_ZC_IPL_BITNUM 2U
#define INTC_IPR4_PWM_RL_IPL_MASK 48U
#define INTC_IPR4_PWM_RL_IPL_BITNUM 4U
#define INTC_IPR4_PWM_F_IPL_MASK 192U
#define INTC_IPR4_PWM_F_IPL_BITNUM 6U
#define INTC_IPR4 *((volatile word *)0x0000F064)
/*** INTC_VBA - Vector Base Address Register; 0x0000F065 ***/
union {
word Word;
} INTC_VBA_STR;
#define INTC_VBA_VECTOR_BASE_ADDRESS0_MASK 1U
#define INTC_VBA_VECTOR_BASE_ADDRESS1_MASK 2U
#define INTC_VBA_VECTOR_BASE_ADDRESS2_MASK 4U
#define INTC_VBA_VECTOR_BASE_ADDRESS3_MASK 8U
#define INTC_VBA_VECTOR_BASE_ADDRESS4_MASK 16U
#define INTC_VBA_VECTOR_BASE_ADDRESS5_MASK 32U
#define INTC_VBA_VECTOR_BASE_ADDRESS6_MASK 64U
#define INTC_VBA_VECTOR_BASE_ADDRESS7_MASK 128U
#define INTC_VBA_VECTOR_BASE_ADDRESS8_MASK 256U
#define INTC_VBA_VECTOR_BASE_ADDRESS9_MASK 512U
#define INTC_VBA_VECTOR_BASE_ADDRESS10_MASK 1024U
#define INTC_VBA_VECTOR_BASE_ADDRESS11_MASK 2048U
#define INTC_VBA_VECTOR_BASE_ADDRESS12_MASK 4096U
#define INTC_VBA_VECTOR_BASE_ADDRESS_MASK 8191U
#define INTC_VBA_VECTOR_BASE_ADDRESS_BITNUM 0U
#define INTC_VBA *((volatile word *)0x0000F065)
/*** INTC_FIM0 - Fast Interrupt 0 Match Register; 0x0000F066 ***/
union {
word Word;
} INTC_FIM0_STR;
#define INTC_FIM0_FAST_INTERRUPT_00_MASK 1U
#define INTC_FIM0_FAST_INTERRUPT_01_MASK 2U
#define INTC_FIM0_FAST_INTERRUPT_02_MASK 4U
#define INTC_FIM0_FAST_INTERRUPT_03_MASK 8U
#define INTC_FIM0_FAST_INTERRUPT_04_MASK 16U
#define INTC_FIM0_FAST_INTERRUPT_05_MASK 32U
#define INTC_FIM0_FAST_INTERRUPT_06_MASK 64U
#define INTC_FIM0_FAST_INTERRUPT_0_MASK 127U
#define INTC_FIM0_FAST_INTERRUPT_0_BITNUM 0U
#define INTC_FIM0 *((volatile word *)0x0000F066)
/*** INTC_FIVAL0 - Fast Interrupt 0 Vector Address Low Register; 0x0000F067 ***/
union {
word Word;
} INTC_FIVAL0_STR;
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW0_MASK 1U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW1_MASK 2U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW2_MASK 4U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW3_MASK 8U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW4_MASK 16U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW5_MASK 32U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW6_MASK 64U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW7_MASK 128U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW8_MASK 256U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW9_MASK 512U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW10_MASK 1024U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW11_MASK 2048U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW12_MASK 4096U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW13_MASK 8192U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW14_MASK 16384U
#define INTC_FIVAL0_FAST_INTERRUPT_0_VECTOR_ADDRESS_LOW15_MASK 32768U
#define INTC_FIVAL0 *((volatile word *)0x0000F067)
/*** INTC_FIVAH0 - Fast Interrupt 0 Vector Address High Register; 0x0000F068 ***/
union {
word Word;
} INTC_FIVAH0_STR;
#define INTC_FIVAH0_FAST_INTERRUPT_0_VECTOR_ADDRESS_HIGH0_MASK 1U
#define INTC_FIVAH0_FAST_INTERRUPT_0_VECTOR_ADDRESS_HIGH1_MASK 2U
#define INTC_FIVAH0_FAST_INTERRUPT_0_VECTOR_ADDRESS_HIGH2_MASK 4U
#define INTC_FIVAH0_FAST_INTERRUPT_0_VECTOR_ADDRESS_HIGH3_MASK 8U
#define INTC_FIVAH0_FAST_INTERRUPT_0_VECTOR_ADDRESS_HIGH4_MASK 16U
#define INTC_FIVAH0_FAST_INTERRUPT_0_VECTOR_ADDRESS_HIGH_MASK 31U
#define INTC_FIVAH0_FAST_INTERRUPT_0_VECTOR_ADDRESS_HIGH_BITNUM 0U
#define INTC_FIVAH0 *((volatile word *)0x0000F068)
/*** INTC_FIM1 - Fast Interrupt 1 Match Register; 0x0000F069 ***/
union {
word Word;
} INTC_FIM1_STR;
#define INTC_FIM1_FAST_INTERRUPT_10_MASK 1U
#define INTC_FIM1_FAST_INTERRUPT_11_MASK 2U
#define INTC_FIM1_FAST_INTERRUPT_12_MASK 4U
#define INTC_FIM1_FAST_INTERRUPT_13_MASK 8U
#define INTC_FIM1_FAST_INTERRUPT_14_MASK 16U
#define INTC_FIM1_FAST_INTERRUPT_15_MASK 32U
#define INTC_FIM1_FAST_INTERRUPT_16_MASK 64U
#define INTC_FIM1_FAST_INTERRUPT_1_MASK 127U
#define INTC_FIM1_FAST_INTERRUPT_1_BITNUM 0U
#define INTC_FIM1 *((volatile word *)0x0000F069)
/*** INTC_FIVAL1 - Fast Interrupt 1 Vector Address Low Register; 0x0000F06A ***/
union {
word Word;
} INTC_FIVAL1_STR;
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW0_MASK 1U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW1_MASK 2U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW2_MASK 4U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW3_MASK 8U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW4_MASK 16U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW5_MASK 32U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW6_MASK 64U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW7_MASK 128U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW8_MASK 256U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW9_MASK 512U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW10_MASK 1024U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW11_MASK 2048U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW12_MASK 4096U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW13_MASK 8192U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW14_MASK 16384U
#define INTC_FIVAL1_FAST_INTERRUPT_1_VECTOR_ADDRESS_LOW15_MASK 32768U
#define INTC_FIVAL1 *((volatile word *)0x0000F06A)
/*** INTC_FIVAH1 - Fast Interrupt 1 Vector Address High Register; 0x0000F06B ***/
union {
word Word;
} INTC_FIVAH1_STR;
#define INTC_FIVAH1_FAST_INTERRUPT_1_VECTOR_ADDRESS_HIGH0_MASK 1U
#define INTC_FIVAH1_FAST_INTERRUPT_1_VECTOR_ADDRESS_HIGH1_MASK 2U
#define INTC_FIVAH1_FAST_INTERRUPT_1_VECTOR_ADDRESS_HIGH2_MASK 4U
#define INTC_FIVAH1_FAST_INTERRUPT_1_VECTOR_ADDRESS_HIGH3_MASK 8U
#define INTC_FIVAH1_FAST_INTERRUPT_1_VECTOR_ADDRESS_HIGH4_MASK 16U
#define INTC_FIVAH1_FAST_INTERRUPT_1_VECTOR_ADDRESS_HIGH_MASK 31U
#define INTC_FIVAH1_FAST_IN⌨️ 快捷键说明
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