io_map.h

BLDC电机控制源代码

  #define TMR2_COMSCR_CL1_MASK          3U
  #define TMR2_COMSCR_CL1_BITNUM        0U
  #define TMR2_COMSCR_CL2_MASK          12U
  #define TMR2_COMSCR_CL2_BITNUM        2U
  #define TMR2_COMSCR_TCF_1_MASK        48U
  #define TMR2_COMSCR_TCF_1_BITNUM      4U
  #define TMR2_COMSCR_DBG_EN_MASK       49152U
  #define TMR2_COMSCR_DBG_EN_BITNUM     14U
  #define TMR2_COMSCR                   *((volatile word *)0x0000F02A)


  word Reserved0[5];                   /* Reserved (unused) registers */

} TMR2_PRPH;

/******************************************
*** Peripheral TMR3
*******************************************/
typedef volatile struct {
  /*** TMR3_CMP1 - Timer Channel 3 Compare Register #1; 0x0000F030 ***/
  union {
    word Word;
  } TMR3_CMP1_STR;
  
  #define TMR3_CMP1                     *((volatile word *)0x0000F030)


  /*** TMR3_CMP2 - Timer Channel 3 Compare Register #2; 0x0000F031 ***/
  union {
    word Word;
  } TMR3_CMP2_STR;
  
  #define TMR3_CMP2                     *((volatile word *)0x0000F031)


  /*** TMR3_CAP - Timer Channel 3 Capture Register; 0x0000F032 ***/
  union {
    word Word;
  } TMR3_CAP_STR;
  
  #define TMR3_CAP                      *((volatile word *)0x0000F032)


  /*** TMR3_LOAD - Timer Channel 3 Load Register; 0x0000F033 ***/
  union {
    word Word;
  } TMR3_LOAD_STR;
  
  #define TMR3_LOAD_LOAD0_MASK          1U
  #define TMR3_LOAD_LOAD1_MASK          2U
  #define TMR3_LOAD_LOAD2_MASK          4U
  #define TMR3_LOAD_LOAD3_MASK          8U
  #define TMR3_LOAD_LOAD4_MASK          16U
  #define TMR3_LOAD_LOAD5_MASK          32U
  #define TMR3_LOAD_LOAD6_MASK          64U
  #define TMR3_LOAD_LOAD7_MASK          128U
  #define TMR3_LOAD_LOAD8_MASK          256U
  #define TMR3_LOAD_LOAD9_MASK          512U
  #define TMR3_LOAD_LOAD10_MASK         1024U
  #define TMR3_LOAD_LOAD11_MASK         2048U
  #define TMR3_LOAD_LOAD12_MASK         4096U
  #define TMR3_LOAD_LOAD13_MASK         8192U
  #define TMR3_LOAD_LOAD14_MASK         16384U
  #define TMR3_LOAD_LOAD15_MASK         32768U
  #define TMR3_LOAD                     *((volatile word *)0x0000F033)


  /*** TMR3_HOLD - Timer Channel 3 Hold Register; 0x0000F034 ***/
  union {
    word Word;
  } TMR3_HOLD_STR;
  
  #define TMR3_HOLD_HOLD0_MASK          1U
  #define TMR3_HOLD_HOLD1_MASK          2U
  #define TMR3_HOLD_HOLD2_MASK          4U
  #define TMR3_HOLD_HOLD3_MASK          8U
  #define TMR3_HOLD_HOLD4_MASK          16U
  #define TMR3_HOLD_HOLD5_MASK          32U
  #define TMR3_HOLD_HOLD6_MASK          64U
  #define TMR3_HOLD_HOLD7_MASK          128U
  #define TMR3_HOLD_HOLD8_MASK          256U
  #define TMR3_HOLD_HOLD9_MASK          512U
  #define TMR3_HOLD_HOLD10_MASK         1024U
  #define TMR3_HOLD_HOLD11_MASK         2048U
  #define TMR3_HOLD_HOLD12_MASK         4096U
  #define TMR3_HOLD_HOLD13_MASK         8192U
  #define TMR3_HOLD_HOLD14_MASK         16384U
  #define TMR3_HOLD_HOLD15_MASK         32768U
  #define TMR3_HOLD                     *((volatile word *)0x0000F034)


  /*** TMR3_CNTR - Timer Channel 3 Counter Register; 0x0000F035 ***/
  union {
    word Word;
  } TMR3_CNTR_STR;
  
  #define TMR3_CNTR                     *((volatile word *)0x0000F035)


  /*** TMR3_CTRL - Timer Channel 3 Control Register; 0x0000F036 ***/
  union {
    word Word;
  } TMR3_CTRL_STR;
  
  #define TMR3_CTRL_OM0_MASK            1U
  #define TMR3_CTRL_OM1_MASK            2U
  #define TMR3_CTRL_OM2_MASK            4U
  #define TMR3_CTRL_Co_INIT_MASK        8U
  #define TMR3_CTRL_DIR_MASK            16U
  #define TMR3_CTRL_LENGTH_MASK         32U
  #define TMR3_CTRL_ONCE_MASK           64U
  #define TMR3_CTRL_SCS0_MASK           128U
  #define TMR3_CTRL_SCS1_MASK           256U
  #define TMR3_CTRL_PCS0_MASK           512U
  #define TMR3_CTRL_PCS1_MASK           1024U
  #define TMR3_CTRL_PCS2_MASK           2048U
  #define TMR3_CTRL_PCS3_MASK           4096U
  #define TMR3_CTRL_CM0_MASK            8192U
  #define TMR3_CTRL_CM1_MASK            16384U
  #define TMR3_CTRL_CM2_MASK            32768U
  #define TMR3_CTRL_OM_MASK             7U
  #define TMR3_CTRL_OM_BITNUM           0U
  #define TMR3_CTRL_SCS_MASK            384U
  #define TMR3_CTRL_SCS_BITNUM          7U
  #define TMR3_CTRL_PCS_MASK            7680U
  #define TMR3_CTRL_PCS_BITNUM          9U
  #define TMR3_CTRL_CM_MASK             57344U
  #define TMR3_CTRL_CM_BITNUM           13U
  #define TMR3_CTRL                     *((volatile word *)0x0000F036)


  /*** TMR3_SCR - Timer Channel 3 Status and Control Register; 0x0000F037 ***/
  union {
    word Word;
  } TMR3_SCR_STR;
  
  #define TMR3_SCR_OEN_MASK             1U
  #define TMR3_SCR_OPS_MASK             2U
  #define TMR3_SCR_FORCE_MASK           4U
  #define TMR3_SCR_VAL_MASK             8U
  #define TMR3_SCR_EEOF_MASK            16U
  #define TMR3_SCR_MSTR_MASK            32U
  #define TMR3_SCR_Capture_Mode0_MASK   64U
  #define TMR3_SCR_Capture_Mode1_MASK   128U
  #define TMR3_SCR_INPUT_MASK           256U
  #define TMR3_SCR_IPS_MASK             512U
  #define TMR3_SCR_IEFIE_MASK           1024U
  #define TMR3_SCR_IEF_MASK             2048U
  #define TMR3_SCR_TOFIE_MASK           4096U
  #define TMR3_SCR_TOF_MASK             8192U
  #define TMR3_SCR_TCFIE_MASK           16384U
  #define TMR3_SCR_TCF_MASK             32768U
  #define TMR3_SCR_Capture_Mode_MASK    192U
  #define TMR3_SCR_Capture_Mode_BITNUM  6U
  #define TMR3_SCR                      *((volatile word *)0x0000F037)


  /*** TMR3_CMPLD1 - Timer Channel 3 Comparator Load Register 1; 0x0000F038 ***/
  union {
    word Word;
  } TMR3_CMPLD1_STR;
  
  #define TMR3_CMPLD1_COMPARATOR_LOAD_10_MASK 1U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_11_MASK 2U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_12_MASK 4U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_13_MASK 8U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_14_MASK 16U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_15_MASK 32U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_16_MASK 64U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_17_MASK 128U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_18_MASK 256U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_19_MASK 512U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_110_MASK 1024U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_111_MASK 2048U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_112_MASK 4096U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_113_MASK 8192U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_114_MASK 16384U
  #define TMR3_CMPLD1_COMPARATOR_LOAD_115_MASK 32768U
  #define TMR3_CMPLD1                   *((volatile word *)0x0000F038)


  /*** TMR3_CMPLD2 - Timer Channel 3 Comparator Load Register 2; 0x0000F039 ***/
  union {
    word Word;
  } TMR3_CMPLD2_STR;
  
  #define TMR3_CMPLD2_COMPARATOR_LOAD_20_MASK 1U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_21_MASK 2U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_22_MASK 4U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_23_MASK 8U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_24_MASK 16U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_25_MASK 32U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_26_MASK 64U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_27_MASK 128U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_28_MASK 256U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_29_MASK 512U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_210_MASK 1024U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_211_MASK 2048U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_212_MASK 4096U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_213_MASK 8192U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_214_MASK 16384U
  #define TMR3_CMPLD2_COMPARATOR_LOAD_215_MASK 32768U
  #define TMR3_CMPLD2                   *((volatile word *)0x0000F039)


  /*** TMR3_COMSCR - Timer Channel 3 Comparator Status and Control Register; 0x0000F03A ***/
  union {
    word Word;
  } TMR3_COMSCR_STR;
  
  #define TMR3_COMSCR_CL10_MASK         1U
  #define TMR3_COMSCR_CL11_MASK         2U
  #define TMR3_COMSCR_CL20_MASK         4U
  #define TMR3_COMSCR_CL21_MASK         8U
  #define TMR3_COMSCR_TCF1_MASK         16U
  #define TMR3_COMSCR_TCF2_MASK         32U
  #define TMR3_COMSCR_TCF1EN_MASK       64U
  #define TMR3_COMSCR_TCF2EN_MASK       128U
  #define TMR3_COMSCR_DBG_EN0_MASK      16384U
  #define TMR3_COMSCR_DBG_EN1_MASK      32768U
  #define TMR3_COMSCR_CL1_MASK          3U
  #define TMR3_COMSCR_CL1_BITNUM        0U
  #define TMR3_COMSCR_CL2_MASK          12U
  #define TMR3_COMSCR_CL2_BITNUM        2U
  #define TMR3_COMSCR_TCF_1_MASK        48U
  #define TMR3_COMSCR_TCF_1_BITNUM      4U
  #define TMR3_COMSCR_DBG_EN_MASK       49152U
  #define TMR3_COMSCR_DBG_EN_BITNUM     14U
  #define TMR3_COMSCR                   *((volatile word *)0x0000F03A)


  word Reserved0[5];                   /* Reserved (unused) registers */

} TMR3_PRPH;

/******************************************
*** Peripheral PWM
*******************************************/
typedef volatile struct {
  /*** PWM_PMCTL - PWM control register; 0x0000F040 ***/
  union {
    word Word;
  } PWM_PMCTL_STR;
  
  #define PWM_PMCTL_PWMEN_MASK          1U
  #define PWM_PMCTL_LDOK_MASK           2U
  #define PWM_PMCTL_PWMF_MASK           16U
  #define PWM_PMCTL_PWMRIE_MASK         32U
  #define PWM_PMCTL_PRSC0_MASK          64U
  #define PWM_PMCTL_PRSC1_MASK          128U
  #define PWM_PMCTL_IPOL0_MASK          256U
  #define PWM_PMCTL_IPOL1_MASK          512U
  #define PWM_PMCTL_IPOL2_MASK          1024U
  #define PWM_PMCTL_HALF_MASK           2048U
  #define PWM_PMCTL_LDFQ0_MASK          4096U
  #define PWM_PMCTL_LDFQ1_MASK          8192U
  #define PWM_PMCTL_LDFQ2_MASK          16384U
  #define PWM_PMCTL_LDFQ3_MASK          32768U
  #define PWM_PMCTL_PRSC_MASK           192U
  #define PWM_PMCTL_PRSC_BITNUM         6U
  #define PWM_PMCTL_IPOL_MASK           1792U
  #define PWM_PMCTL_IPOL_BITNUM         8U
  #define PWM_PMCTL_LDFQ_MASK           61440U
  #define PWM_PMCTL_LDFQ_BITNUM         12U
  #define PWM_PMCTL                     *((volatile word *)0x0000F040)


  /*** PWM_PMFCTL - PWM fault control register; 0x0000F041 ***/
  union {
    word Word;
  } PWM_PMFCTL_STR;
  
  #define PWM_PMFCTL_FMODE0_MASK        1U
  #define PWM_PMFCTL_FIE0_MASK          2U
  #define PWM_PMFCTL_FMODE1_MASK        4U
  #define PWM_PMFCTL_FIE1_MASK          8U
  #define PWM_PMFCTL_FMODE2_MASK        16U
  #define PWM_PMFCTL_FIE2_MASK          32U
  #define PWM_PMFCTL_FMODE3_MASK        64U
  #define PWM_PMFCTL_FIE3_MASK          128U
  #define PWM_PMFCTL                    *((volatile word *)0x0000F041)


  /*** PWM_PMFSA - PWM fault status acknowledge; 0x0000F042 ***/
  union {
    word Word;
  } PWM_PMFSA_STR;
  
  #define PWM_PMFSA_DT0_FTACK0_MASK     1U
  #define PWM_PMFSA_DT1_MASK            2U
  #define PWM_PMFSA_DT2_FTACK1_MASK     4U
  #define PWM_PMFSA_DT3_MASK            8U
  #define PWM_PMFSA_DT4_FTACK2_MASK     16U
  #define PWM_PMFSA_DT5_MASK            32U
  #define PWM_PMFSA_FTACK3_MASK         64U
  #define PWM_PMFSA_FFLAG0_MASK         256U
  #define PWM_PMFSA_FPIN0_MASK          512U
  #define PWM_PMFSA_FFLAG1_MASK         1024U
  #define PWM_PMFSA_FPIN1_MASK          2048U
  #define PWM_PMFSA_FFLAG2_MASK         4096U
  #define PWM_PMFSA_FPIN2_MASK          8192U
  #define PWM_PMFSA_FFLAG3_MASK         16384U
  #define PWM_PMFSA_FPIN3_MASK          32768U
  #define PWM_PMFSA                     *((volatile word *)0x0000F042)


  /*** PWM_PMOUT - PWM output control register; 0x0000F043 ***/
  union {
    word Word;
  } PWM_PMOUT_STR;
  
  #define PWM_PMOUT_OUT0_MASK           1U
  #define PWM_PMOUT_OUT1_MASK           2U
  #define PWM_PMOUT_OUT2_MASK           4U
  #define PWM_PMOUT_OUT3_MASK           8U
  #define PWM_PMOUT_OUT4_MASK           16U
  #define PWM_PMOUT_OUT5_MASK           32U
  #define PWM_PMOUT_OUTCTL0_MASK        256U
  #define PWM_PMOUT_OUTCTL1_MASK        512U
  #define PWM_PMOUT_OUTCTL2_MASK        1024U
  #define PWM_PMOUT_OUTCTL3_MASK        2048U
  #define PWM_PMOUT_OUTCTL4_MASK        4096U
  #define PWM_PMOUT_OUTCTL5_MASK        8192U
  #define PWM_PMOUT_PAD_EN_MASK         32768U
  #define PWM_PMOUT_OUT_MASK            63U
  #define PWM_PMOUT_OUT_BITNUM          0U
  #define PWM_PMOUT_OUTCTL_MASK         16128U
  #define PWM_PMOUT_OUTCTL_BITNUM       8U
  #define PWM_PMOUT                     *((volatile word *)0x0000F043)


  /*** PWM_PMCNT - PWM counter register; 0x0000F044 ***/
  union {
    word Word;
  } PWM_PMCNT_STR;
  
  #define PWM_PMCNT_CNT0_MASK           1U
  #define PWM_PMCNT_CNT1_MASK           2U
  #define PWM_PMCNT_CNT2_MASK           4U
  #define PWM_PMCNT_CNT3_MASK           8U