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C51 COMPILER V8.05a   2_01_12G                                                             06/07/2007 19:40:26 PAGE 1   


C51 COMPILER V8.05a, COMPILATION OF MODULE 2_01_12G
OBJECT MODULE PLACED IN 2_01_12G.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE 2_01_12G.C OPTIMIZE(6,SPEED) BROWSE DEBUG OBJECTEXTEND CODE LISTINCLUDE SYM
                    -BOLS

line level    source

   1          /*------------------------------------------------------------------*-
   2          
   3             2_01_12g.C (v1.00) 
   4          
   5            ------------------------------------------------------------------
   6          
   7             *** THIS IS A SCHEDULER FOR STANDARD 8051 / 8052 ***
   8          
   9             *** Uses T2 for timing, 16-bit auto reload ***
  10             *** 12 MHz oscillator -> 1 ms (precise) tick interval ***
  11          
  12          
  13             COPYRIGHT
  14             ---------
  15          
  16             This code is from the book:
  17          
  18             PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont 
  19             [Pearson Education, 2001; ISBN: 0-201-33138-1].
  20          
  21             This code is copyright (c) 2001 by Michael J. Pont.
  22           
  23             See book for copyright details and other information.
  24          
  25          -*------------------------------------------------------------------*/
  26          
  27          #include "2_01_12g.h"
   1      =1  /*------------------------------------------------------------------*-
   2      =1    
   3      =1     2_01_12g.h (v1.00) 
   4      =1  
   5      =1    ------------------------------------------------------------------
   6      =1  
   7      =1     - see 2_01_12g.C for details
   8      =1  
   9      =1  
  10      =1     COPYRIGHT
  11      =1     ---------
  12      =1  
  13      =1     This code is from the book:
  14      =1  
  15      =1     PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont 
  16      =1     [Pearson Education, 2001; ISBN: 0-201-33138-1].
  17      =1  
  18      =1     This code is copyright (c) 2001 by Michael J. Pont.
  19      =1   
  20      =1     See book for copyright details and other information.
  21      =1  
  22      =1  -*------------------------------------------------------------------*/
  23      =1  
  24      =1  #include "Main.h"
   1      =2  /*------------------------------------------------------------------*-
   2      =2  
   3      =2     Main.H (v1.00)
C51 COMPILER V8.05a   2_01_12G                                                             06/07/2007 19:40:26 PAGE 2   

   4      =2  
   5      =2    ------------------------------------------------------------------
   6      =2     
   7      =2     'Project Header' (see Chap 9) for project LED_TIME (see Chap 21)
   8      =2  
   9      =2  
  10      =2     COPYRIGHT
  11      =2     ---------
  12      =2  
  13      =2     This code is from the book:
  14      =2  
  15      =2     PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont 
  16      =2     [Pearson Education, 2001; ISBN: 0-201-33138-1].
  17      =2  
  18      =2     This code is copyright (c) 2001 by Michael J. Pont.
  19      =2   
  20      =2     See book for copyright details and other information.
  21      =2  
  22      =2  -*------------------------------------------------------------------*/
  23      =2  
  24      =2  #ifndef _MAIN_H
  25      =2  #define _MAIN_H
  26      =2  
  27      =2  //------------------------------------------------------------------
  28      =2  // WILL NEED TO EDIT THIS SECTION FOR EVERY PROJECT
  29      =2  //------------------------------------------------------------------
  30      =2  
  31      =2  // Must include the appropriate microcontroller header file here
  32      =2  #include <AT89x52.h>
   1      =3  /*--------------------------------------------------------------------------
   2      =3  AT89X52.H
   3      =3  
   4      =3  Header file for the low voltage Flash Atmel AT89C52 and AT89LV52.
   5      =3  Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc.
   6      =3  All rights reserved.
   7      =3  --------------------------------------------------------------------------*/
   8      =3  
   9      =3  #ifndef __AT89X52_H__
  10      =3  #define __AT89X52_H__
  11      =3  
  12      =3  /*------------------------------------------------
  13      =3  Byte Registers
  14      =3  ------------------------------------------------*/
  15      =3  sfr P0      = 0x80;
  16      =3  sfr SP      = 0x81;
  17      =3  sfr DPL     = 0x82;
  18      =3  sfr DPH     = 0x83;
  19      =3  sfr PCON    = 0x87;
  20      =3  sfr TCON    = 0x88;
  21      =3  sfr TMOD    = 0x89;
  22      =3  sfr TL0     = 0x8A;
  23      =3  sfr TL1     = 0x8B;
  24      =3  sfr TH0     = 0x8C;
  25      =3  sfr TH1     = 0x8D;
  26      =3  sfr P1      = 0x90;
  27      =3  sfr SCON    = 0x98;
  28      =3  sfr SBUF    = 0x99;
  29      =3  sfr P2      = 0xA0;
  30      =3  sfr IE      = 0xA8;
  31      =3  sfr P3      = 0xB0;
  32      =3  sfr IP      = 0xB8;
  33      =3  sfr T2CON   = 0xC8;
C51 COMPILER V8.05a   2_01_12G                                                             06/07/2007 19:40:26 PAGE 3   

  34      =3  sfr T2MOD   = 0xC9;
  35      =3  sfr RCAP2L  = 0xCA;
  36      =3  sfr RCAP2H  = 0xCB;
  37      =3  sfr TL2     = 0xCC;
  38      =3  sfr TH2     = 0xCD;
  39      =3  sfr PSW     = 0xD0;
  40      =3  sfr ACC     = 0xE0;
  41      =3  sfr B       = 0xF0;
  42      =3  
  43      =3  /*------------------------------------------------
  44      =3  P0 Bit Registers
  45      =3  ------------------------------------------------*/
  46      =3  sbit P0_0 = 0x80;
  47      =3  sbit P0_1 = 0x81;
  48      =3  sbit P0_2 = 0x82;
  49      =3  sbit P0_3 = 0x83;
  50      =3  sbit P0_4 = 0x84;
  51      =3  sbit P0_5 = 0x85;
  52      =3  sbit P0_6 = 0x86;
  53      =3  sbit P0_7 = 0x87;
  54      =3  
  55      =3  /*------------------------------------------------
  56      =3  PCON Bit Values
  57      =3  ------------------------------------------------*/
  58      =3  #define IDL_    0x01
  59      =3  
  60      =3  #define STOP_   0x02
  61      =3  #define PD_     0x02    /* Alternate definition */
  62      =3  
  63      =3  #define GF0_    0x04
  64      =3  #define GF1_    0x08
  65      =3  #define SMOD_   0x80
  66      =3  
  67      =3  /*------------------------------------------------
  68      =3  TCON Bit Registers
  69      =3  ------------------------------------------------*/
  70      =3  sbit IT0  = 0x88;
  71      =3  sbit IE0  = 0x89;
  72      =3  sbit IT1  = 0x8A;
  73      =3  sbit IE1  = 0x8B;
  74      =3  sbit TR0  = 0x8C;
  75      =3  sbit TF0  = 0x8D;
  76      =3  sbit TR1  = 0x8E;
  77      =3  sbit TF1  = 0x8F;
  78      =3  
  79      =3  /*------------------------------------------------
  80      =3  TMOD Bit Values
  81      =3  ------------------------------------------------*/
  82      =3  #define T0_M0_   0x01
  83      =3  #define T0_M1_   0x02
  84      =3  #define T0_CT_   0x04
  85      =3  #define T0_GATE_ 0x08
  86      =3  #define T1_M0_   0x10
  87      =3  #define T1_M1_   0x20
  88      =3  #define T1_CT_   0x40
  89      =3  #define T1_GATE_ 0x80
  90      =3  
  91      =3  #define T1_MASK_ 0xF0
  92      =3  #define T0_MASK_ 0x0F
  93      =3  
  94      =3  /*------------------------------------------------
  95      =3  P1 Bit Registers
C51 COMPILER V8.05a   2_01_12G                                                             06/07/2007 19:40:26 PAGE 4   

  96      =3  ------------------------------------------------*/
  97      =3  sbit P1_0 = 0x90;
  98      =3  sbit P1_1 = 0x91;
  99      =3  sbit P1_2 = 0x92;
 100      =3  sbit P1_3 = 0x93;
 101      =3  sbit P1_4 = 0x94;
 102      =3  sbit P1_5 = 0x95;
 103      =3  sbit P1_6 = 0x96;
 104      =3  sbit P1_7 = 0x97;
 105      =3  
 106      =3  sbit T2   = 0x90;       /* External input to Timer/Counter 2, clock out */
 107      =3  sbit T2EX = 0x91;       /* Timer/Counter 2 capture/reload trigger & dir ctl */
 108      =3  
 109      =3  /*------------------------------------------------
 110      =3  SCON Bit Registers
 111      =3  ------------------------------------------------*/
 112      =3  sbit RI   = 0x98;
 113      =3  sbit TI   = 0x99;
 114      =3  sbit RB8  = 0x9A;
 115      =3  sbit TB8  = 0x9B;
 116      =3  sbit REN  = 0x9C;
 117      =3  sbit SM2  = 0x9D;
 118      =3  sbit SM1  = 0x9E;
 119      =3  sbit SM0  = 0x9F;
 120      =3  
 121      =3  /*------------------------------------------------
 122      =3  P2 Bit Registers
 123      =3  ------------------------------------------------*/
 124      =3  sbit P2_0 = 0xA0;
 125      =3  sbit P2_1 = 0xA1;
 126      =3  sbit P2_2 = 0xA2;
 127      =3  sbit P2_3 = 0xA3;
 128      =3  sbit P2_4 = 0xA4;
 129      =3  sbit P2_5 = 0xA5;
 130      =3  sbit P2_6 = 0xA6;
 131      =3  sbit P2_7 = 0xA7;
 132      =3  
 133      =3  /*------------------------------------------------
 134      =3  IE Bit Registers
 135      =3  ------------------------------------------------*/
 136      =3  sbit EX0  = 0xA8;       /* 1=Enable External interrupt 0 */
 137      =3  sbit ET0  = 0xA9;       /* 1=Enable Timer 0 interrupt */
 138      =3  sbit EX1  = 0xAA;       /* 1=Enable External interrupt 1 */
 139      =3  sbit ET1  = 0xAB;       /* 1=Enable Timer 1 interrupt */
 140      =3  sbit ES   = 0xAC;       /* 1=Enable Serial port interrupt */
 141      =3  sbit ET2  = 0xAD;       /* 1=Enable Timer 2 interrupt */
 142      =3  
 143      =3  sbit EA   = 0xAF;       /* 0=Disable all interrupts */
 144      =3  
 145      =3  /*------------------------------------------------
 146      =3  P3 Bit Registers (Mnemonics & Ports)
 147      =3  ------------------------------------------------*/
 148      =3  sbit P3_0 = 0xB0;
 149      =3  sbit P3_1 = 0xB1;
 150      =3  sbit P3_2 = 0xB2;
 151      =3  sbit P3_3 = 0xB3;
 152      =3  sbit P3_4 = 0xB4;
 153      =3  sbit P3_5 = 0xB5;
 154      =3  sbit P3_6 = 0xB6;
 155      =3  sbit P3_7 = 0xB7;
 156      =3  
 157      =3  sbit RXD  = 0xB0;       /* Serial data input */
C51 COMPILER V8.05a   2_01_12G                                                             06/07/2007 19:40:26 PAGE 5   

 158      =3  sbit TXD  = 0xB1;       /* Serial data output */
 159      =3  sbit INT0 = 0xB2;       /* External interrupt 0 */
 160      =3  sbit INT1 = 0xB3;       /* External interrupt 1 */
 161      =3  sbit T0   = 0xB4;       /* Timer 0 external input */
 162      =3  sbit T1   = 0xB5;       /* Timer 1 external input */
 163      =3  sbit WR   = 0xB6;       /* External data memory write strobe */
 164      =3  sbit RD   = 0xB7;       /* External data memory read strobe */
 165      =3  
 166      =3  /*------------------------------------------------
 167      =3  IP Bit Registers
 168      =3  ------------------------------------------------*/
 169      =3  sbit PX0  = 0xB8;
 170      =3  sbit PT0  = 0xB9;
 171      =3  sbit PX1  = 0xBA;
 172      =3  sbit PT1  = 0xBB;
 173      =3  sbit PS   = 0xBC;
 174      =3  sbit PT2  = 0xBD;
 175      =3  
 176      =3  /*------------------------------------------------
 177      =3  T2CON Bit Registers
 178      =3  ------------------------------------------------*/
 179      =3  sbit CP_RL2= 0xC8;      /* 0=Reload, 1=Capture select */
 180      =3  sbit C_T2 = 0xC9;       /* 0=Timer, 1=Counter */
 181      =3  sbit TR2  = 0xCA;       /* 0=Stop timer, 1=Start timer */
 182      =3  sbit EXEN2= 0xCB;       /* Timer 2 external enable */
 183      =3  sbit TCLK = 0xCC;       /* 0=Serial clock uses Timer 1 overflow, 1=Timer 2 */
 184      =3  sbit RCLK = 0xCD;       /* 0=Serial clock uses Timer 1 overflow, 1=Timer 2 */
 185      =3  sbit EXF2 = 0xCE;       /* Timer 2 external flag */
 186      =3  sbit TF2  = 0xCF;       /* Timer 2 overflow flag */
 187      =3  
 188      =3  /*------------------------------------------------
 189      =3  T2MOD Bit Values
 190      =3  ------------------------------------------------*/
 191      =3  #define DCEN_   0x01    /* 1=Timer 2 can be configured as up/down counter */
 192      =3  #define T2OE_   0x02    /* Timer 2 output enable */
 193      =3  
 194      =3  /*------------------------------------------------
 195      =3  PSW Bit Registers
 196      =3  ------------------------------------------------*/
 197      =3  sbit P    = 0xD0;
 198      =3  sbit FL   = 0xD1;
 199      =3  sbit OV   = 0xD2;
 200      =3  sbit RS0  = 0xD3;
 201      =3  sbit RS1  = 0xD4;
 202      =3  sbit F0   = 0xD5;
 203      =3  sbit AC   = 0xD6;
 204      =3  sbit CY   = 0xD7;
 205      =3  
 206      =3  /*------------------------------------------------
 207      =3  Interrupt Vectors:
 208      =3  Interrupt Address = (Number * 8) + 3
 209      =3  ------------------------------------------------*/
 210      =3  #define IE0_VECTOR      0  /* 0x03 External Interrupt 0 */
 211      =3  #define TF0_VECTOR      1  /* 0x0B Timer 0 */
 212      =3  #define IE1_VECTOR      2  /* 0x13 External Interrupt 1 */
 213      =3  #define TF1_VECTOR      3  /* 0x1B Timer 1 */
 214      =3  #define SIO_VECTOR      4  /* 0x23 Serial port */
 215      =3  
 216      =3  #define TF2_VECTOR      5  /* 0x2B Timer 2 */
 217      =3  #define EX2_VECTOR      5  /* 0x2B External Interrupt 2 */
 218      =3  
 219      =3  #endif
C51 COMPILER V8.05a   2_01_12G                                                             06/07/2007 19:40:26 PAGE 6   

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