shift_reg.v

一种由可编程逻辑器件集成的数字滤波器的设计

// megafunction wizard: %ALTSHIFT_TAPS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altshift_taps 

// ============================================================
// File Name: shift_reg.v
// Megafunction Name(s):
// 			altshift_taps
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************


//Copyright (C) 1991-2002 Altera Corporation
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
//support information,  device programming or simulation file,  and any other
//associated  documentation or information  provided by  Altera  or a partner
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
//other  use  of such  megafunction  design,  netlist,  support  information,
//device programming or simulation file,  or any other  related documentation
//or information  is prohibited  for  any  other purpose,  including, but not
//limited to  modification,  reverse engineering,  de-compiling, or use  with
//any other  silicon devices,  unless such use is  explicitly  licensed under
//a separate agreement with  Altera  or a megafunction partner.  Title to the
//intellectual property,  including patents,  copyrights,  trademarks,  trade
//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
//support  information,  device programming or simulation file,  or any other
//related documentation or information provided by  Altera  or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.

module shift_reg (
	shiftin,
	clock,
	clken,
	shiftout,
	taps);

	input	[8:0]  shiftin;
	input	  clock;
	input	  clken;
	output	[8:0]  shiftout;
	output	[26:0]  taps;

	wire [26:0] sub_wire0;
	wire [8:0] sub_wire1;
	wire [26:0] taps = sub_wire0[26:0];
	wire [8:0] shiftout = sub_wire1[8:0];

	altshift_taps	altshift_taps_component (
				.clken (clken),
				.clock (clock),
				.shiftin (shiftin),
				.taps (sub_wire0),
				.shiftout (sub_wire1));
	defparam
		altshift_taps_component.width = 9,
		altshift_taps_component.number_of_taps = 3,
		altshift_taps_component.tap_distance = 4;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: WIDTH NUMERIC "9"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "3"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "4"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH NUMERIC "9"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "3"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "4"
// Retrieval info: USED_PORT: shiftin 0 0 9 0 INPUT NODEFVAL shiftin[8..0]
// Retrieval info: USED_PORT: shiftout 0 0 9 0 OUTPUT NODEFVAL shiftout[8..0]
// Retrieval info: USED_PORT: taps 0 0 27 0 OUTPUT NODEFVAL taps[26..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: CONNECT: @shiftin 0 0 9 0 shiftin 0 0 9 0
// Retrieval info: CONNECT: shiftout 0 0 9 0 @shiftout 0 0 9 0
// Retrieval info: CONNECT: taps 0 0 27 0 @taps 0 0 27 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all