at91sam7se512_inc.h

AT91SAM7SE系列IAR编程中外扩NAND的源码。

// *****************************************************************************
// *** Register offset in AT91S_PITC structure ***
#define PITC_PIMR       ( 0) // Period Interval Mode Register
#define PITC_PISR       ( 4) // Period Interval Status Register
#define PITC_PIVR       ( 8) // Period Interval Value Register
#define PITC_PIIR       (12) // Period Interval Image Register
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_WDTC structure ***
#define WDTC_WDCR       ( 0) // Watchdog Control Register
#define WDTC_WDMR       ( 4) // Watchdog Mode Register
#define WDTC_WDSR       ( 8) // Watchdog Status Register
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_VREG structure ***
#define VREG_MR         ( 0) // Voltage Regulator Mode Register
// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
#define AT91C_VREG_PSTDBY         (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_MC structure ***
#define MC_RCR          ( 0) // MC Remap Control Register
#define MC_ASR          ( 4) // MC Abort Status Register
#define MC_AASR         ( 8) // MC Abort Address Status Register
#define MC_PUIA         (16) // MC Protection Unit Area
#define MC_PUP          (80) // MC Protection Unit Peripherals
#define MC_PUER         (84) // MC Protection Unit Enable Register
#define MC0_FMR         (96) // MC Flash Mode Register
#define MC0_FCR         (100) // MC Flash Command Register
#define MC0_FSR         (104) // MC Flash Status Register
#define MC0_VR          (108) // MC Flash Version Register
#define MC1_FMR         (112) // MC Flash Mode Register
#define MC1_FCR         (116) // MC Flash Command Register
#define MC1_FSR         (120) // MC Flash Status Register
#define MC1_VR          (124) // MC Flash Version Register
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_MPU              (0x1 <<  2) // (MC) Memory protection Unit Abort Status
#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- 
#define AT91C_MC_PROT             (0x3 <<  0) // (MC) Protection
#define 	AT91C_MC_PROT_PNAUNA               (0x0) // (MC) Privilege: No Access, User: No Access
#define 	AT91C_MC_PROT_PRWUNA               (0x1) // (MC) Privilege: Read/Write, User: No Access
#define 	AT91C_MC_PROT_PRWURO               (0x2) // (MC) Privilege: Read/Write, User: Read Only
#define 	AT91C_MC_PROT_PRWURW               (0x3) // (MC) Privilege: Read/Write, User: Read/Write
#define AT91C_MC_SIZE             (0xF <<  4) // (MC) Internal Area Size
#define 	AT91C_MC_SIZE_1KB                  (0x0 <<  4) // (MC) Area size 1KByte
#define 	AT91C_MC_SIZE_2KB                  (0x1 <<  4) // (MC) Area size 2KByte
#define 	AT91C_MC_SIZE_4KB                  (0x2 <<  4) // (MC) Area size 4KByte
#define 	AT91C_MC_SIZE_8KB                  (0x3 <<  4) // (MC) Area size 8KByte
#define 	AT91C_MC_SIZE_16KB                 (0x4 <<  4) // (MC) Area size 16KByte
#define 	AT91C_MC_SIZE_32KB                 (0x5 <<  4) // (MC) Area size 32KByte
#define 	AT91C_MC_SIZE_64KB                 (0x6 <<  4) // (MC) Area size 64KByte
#define 	AT91C_MC_SIZE_128KB                (0x7 <<  4) // (MC) Area size 128KByte
#define 	AT91C_MC_SIZE_256KB                (0x8 <<  4) // (MC) Area size 256KByte
#define 	AT91C_MC_SIZE_512KB                (0x9 <<  4) // (MC) Area size 512KByte
#define 	AT91C_MC_SIZE_1MB                  (0xA <<  4) // (MC) Area size 1MByte
#define 	AT91C_MC_SIZE_2MB                  (0xB <<  4) // (MC) Area size 2MByte
#define 	AT91C_MC_SIZE_4MB                  (0xC <<  4) // (MC) Area size 4MByte
#define 	AT91C_MC_SIZE_8MB                  (0xD <<  4) // (MC) Area size 8MByte
#define 	AT91C_MC_SIZE_16MB                 (0xE <<  4) // (MC) Area size 16MByte
#define 	AT91C_MC_SIZE_64MB                 (0xF <<  4) // (MC) Area size 64MByte
#define AT91C_MC_BA               (0x3FFFF << 10) // (MC) Internal Area Base Address
// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- 
// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- 
#define AT91C_MC_PUEB             (0x1 <<  0) // (MC) Protection Unit enable Bit

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Embedded Flash Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_EFC structure ***
#define EFC_FMR         ( 0) // MC Flash Mode Register
#define EFC_FCR         ( 4) // MC Flash Command Register
#define EFC_FSR         ( 8) // MC Flash Status Register
#define EFC_VR          (12) // MC Flash Version Register
// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register -------- 
#define AT91C_MC_FRDY             (0x1 <<  0) // (EFC) Flash Ready
#define AT91C_MC_LOCKE            (0x1 <<  2) // (EFC) Lock Error
#define AT91C_MC_PROGE            (0x1 <<  3) // (EFC) Programming Error
#define AT91C_MC_NEBP             (0x1 <<  7) // (EFC) No Erase Before Programming
#define AT91C_MC_FWS              (0x3 <<  8) // (EFC) Flash Wait State
#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (EFC) 1 cycle for Read, 2 for Write operations
#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (EFC) 2 cycles for Read, 3 for Write operations
#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (EFC) 3 cycles for Read, 4 for Write operations
#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (EFC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN             (0xFF << 16) // (EFC) Flash Microsecond Cycle Number
// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register -------- 
#define AT91C_MC_FCMD             (0xF <<  0) // (EFC) Flash Command
#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (EFC) Starts the programming of th epage specified by PAGEN.
#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed.
#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (EFC) Set General Purpose NVM bits.
#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (EFC) Clear General Purpose NVM bits.
#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (EFC) Set Security Bit.
#define AT91C_MC_PAGEN            (0x3FF <<  8) // (EFC) Page Number
#define AT91C_MC_KEY              (0xFF << 24) // (EFC) Writing Protect Key
// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register -------- 
#define AT91C_MC_SECURITY         (0x1 <<  4) // (EFC) Security Bit Status
#define AT91C_MC_GPNVM0           (0x1 <<  8) // (EFC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1           (0x1 <<  9) // (EFC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2           (0x1 << 10) // (EFC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3           (0x1 << 11) // (EFC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4           (0x1 << 12) // (EFC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5           (0x1 << 13) // (EFC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6           (0x1 << 14) // (EFC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7           (0x1 << 15) // (EFC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0           (0x1 << 16) // (EFC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1           (0x1 << 17) // (EFC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2           (0x1 << 18) // (EFC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3           (0x1 << 19) // (EFC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4           (0x1 << 20) // (EFC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5           (0x1 << 21) // (EFC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6           (0x1 << 22) // (EFC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7           (0x1 << 23) // (EFC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8           (0x1 << 24) // (EFC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9           (0x1 << 25) // (EFC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10          (0x1 << 26) // (EFC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11          (0x1 << 27) // (EFC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12          (0x1 << 28) // (EFC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13          (0x1 << 29) // (EFC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14          (0x1 << 30) // (EFC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15          (0x1 << 31) // (EFC) Sector 15 Lock Status
// -------- EFC_VR : (EFC Offset: 0xc) EFC version register -------- 
#define AT91C_EFC_VERSION         (0xFFF <<  0) // (EFC) EFC version number
#define AT91C_EFC_MFN             (0x7 << 16) // (EFC) EFC MFN

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
// *****************************************************************************