📄 at91sam7se512.inc
字号:
AT91C_SPI_TD EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data
AT91C_SPI_TPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
;- -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
AT91C_SPI_RDRF EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full
AT91C_SPI_TDRE EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty
AT91C_SPI_MODF EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error
AT91C_SPI_OVRES EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status
AT91C_SPI_ENDRX EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer
AT91C_SPI_ENDTX EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer
AT91C_SPI_RXBUFF EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt
AT91C_SPI_TXBUFE EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt
AT91C_SPI_NSSR EQU (0x1:SHL:8) ;- (SPI) NSSR Interrupt
AT91C_SPI_TXEMPTY EQU (0x1:SHL:9) ;- (SPI) TXEMPTY Interrupt
AT91C_SPI_SPIENS EQU (0x1:SHL:16) ;- (SPI) Enable Status
;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
AT91C_SPI_CPOL EQU (0x1:SHL:0) ;- (SPI) Clock Polarity
AT91C_SPI_NCPHA EQU (0x1:SHL:1) ;- (SPI) Clock Phase
AT91C_SPI_CSAAT EQU (0x1:SHL:3) ;- (SPI) Chip Select Active After Transfer
AT91C_SPI_BITS EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer
AT91C_SPI_BITS_8 EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer
AT91C_SPI_BITS_9 EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer
AT91C_SPI_BITS_10 EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer
AT91C_SPI_BITS_11 EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer
AT91C_SPI_BITS_12 EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer
AT91C_SPI_BITS_13 EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer
AT91C_SPI_BITS_14 EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer
AT91C_SPI_BITS_15 EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer
AT91C_SPI_BITS_16 EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer
AT91C_SPI_SCBR EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate
AT91C_SPI_DLYBS EQU (0xFF:SHL:16) ;- (SPI) Delay Before SPCK
AT91C_SPI_DLYBCT EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Usart
;- *****************************************************************************
^ 0 ;- AT91S_USART
US_CR # 4 ;- Control Register
US_MR # 4 ;- Mode Register
US_IER # 4 ;- Interrupt Enable Register
US_IDR # 4 ;- Interrupt Disable Register
US_IMR # 4 ;- Interrupt Mask Register
US_CSR # 4 ;- Channel Status Register
US_RHR # 4 ;- Receiver Holding Register
US_THR # 4 ;- Transmitter Holding Register
US_BRGR # 4 ;- Baud Rate Generator Register
US_RTOR # 4 ;- Receiver Time-out Register
US_TTGR # 4 ;- Transmitter Time-guard Register
# 20 ;- Reserved
US_FIDI # 4 ;- FI_DI_Ratio Register
US_NER # 4 ;- Nb Errors Register
# 4 ;- Reserved
US_IF # 4 ;- IRDA_FILTER Register
# 176 ;- Reserved
US_RPR # 4 ;- Receive Pointer Register
US_RCR # 4 ;- Receive Counter Register
US_TPR # 4 ;- Transmit Pointer Register
US_TCR # 4 ;- Transmit Counter Register
US_RNPR # 4 ;- Receive Next Pointer Register
US_RNCR # 4 ;- Receive Next Counter Register
US_TNPR # 4 ;- Transmit Next Pointer Register
US_TNCR # 4 ;- Transmit Next Counter Register
US_PTCR # 4 ;- PDC Transfer Control Register
US_PTSR # 4 ;- PDC Transfer Status Register
;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break
AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break
AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out
AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address
AT91C_US_RSTIT EQU (0x1:SHL:13) ;- (USART) Reset Iterations
AT91C_US_RSTNACK EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge
AT91C_US_RETTO EQU (0x1:SHL:15) ;- (USART) Rearm Time-out
AT91C_US_DTREN EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable
AT91C_US_DTRDIS EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable
AT91C_US_RTSEN EQU (0x1:SHL:18) ;- (USART) Request to Send enable
AT91C_US_RTSDIS EQU (0x1:SHL:19) ;- (USART) Request to Send Disable
;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
AT91C_US_USMODE EQU (0xF:SHL:0) ;- (USART) Usart mode
AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock
AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1
AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM)
AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK)
AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits
AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits
AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits
AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits
AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select
AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits
AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit
AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits
AT91C_US_MSBF EQU (0x1:SHL:16) ;- (USART) Bit Order
AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length
AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select
AT91C_US_OVER EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode
AT91C_US_INACK EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge
AT91C_US_DSNACK EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK
AT91C_US_MAX_ITER EQU (0x1:SHL:24) ;- (USART) Number of Repetitions
AT91C_US_FILTER EQU (0x1:SHL:28) ;- (USART) Receive Line Filter
;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break
AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out
AT91C_US_ITERATION EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached
AT91C_US_NACK EQU (0x1:SHL:13) ;- (USART) Non Acknowledge
AT91C_US_RIIC EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag
AT91C_US_DSRIC EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag
AT91C_US_DCDIC EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag
AT91C_US_CTSIC EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag
;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
AT91C_US_RI EQU (0x1:SHL:20) ;- (USART) Image of RI Input
AT91C_US_DSR EQU (0x1:SHL:21) ;- (USART) Image of DSR Input
AT91C_US_DCD EQU (0x1:SHL:22) ;- (USART) Image of DCD Input
AT91C_US_CTS EQU (0x1:SHL:23) ;- (USART) Image of CTS Input
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_SSC
SSC_CR # 4 ;- Control Register
SSC_CMR # 4 ;- Clock Mode Register
# 8 ;- Reserved
SSC_RCMR # 4 ;- Receive Clock ModeRegister
SSC_RFMR # 4 ;- Receive Frame Mode Register
SSC_TCMR # 4 ;- Transmit Clock Mode Register
SSC_TFMR # 4 ;- Transmit Frame Mode Register
SSC_RHR # 4 ;- Receive Holding Register
SSC_THR # 4 ;- Transmit Holding Register
# 8 ;- Reserved
SSC_RSHR # 4 ;- Receive Sync Holding Register
SSC_TSHR # 4 ;- Transmit Sync Holding Register
# 8 ;- Reserved
SSC_SR # 4 ;- Status Register
SSC_IER # 4 ;- Interrupt Enable Register
SSC_IDR # 4 ;- Interrupt Disable Register
SSC_IMR # 4 ;- Interrupt Mask Register
# 176 ;- Reserved
SSC_RPR # 4 ;- Receive Pointer Register
SSC_RCR # 4 ;- Receive Counter Register
SSC_TPR # 4 ;- Transmit Pointer Register
SSC_TCR # 4 ;- Transmit Counter Register
SSC_RNPR # 4 ;- Receive Next Pointer Register
SSC_RNCR # 4 ;- Receive Next Counter Register
SSC_TNPR # 4 ;- Transmit Next Pointer Register
SSC_TNCR # 4 ;- Transmit Next Counter Register
SSC_PTCR # 4 ;- PDC Transfer Control Register
SSC_PTSR # 4 ;- PDC Transfer Status Register
;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
AT91C_SSC_RXEN EQU (0x1:SHL:0) ;- (SSC) Receive Enable
AT91C_SSC_RXDIS EQU (0x1:SHL:1) ;- (SSC) Receive Disable
AT91C_SSC_TXEN EQU (0x1:SHL:8) ;- (SSC) Transmit Enable
AT91C_SSC_TXDIS EQU (0x1:SHL:9) ;- (SSC) Transmit Disable
AT91C_SSC_SWRST EQU (0x1:SHL:15) ;- (SSC) Software Reset
;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
AT91C_SSC_CKS EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection
AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock
AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal
AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin
AT91C_SSC_CKO EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
AT91C_SSC_CKO_NONE EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
AT91C_SSC_CKO_CONTINOUS EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
AT91C_SSC_CKO_DATA_TX EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
AT91C_SSC_CKI EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion
AT91C_SSC_CKG EQU (0x3:SHL:6) ;- (SSC) Receive/Transmit Clock Gating Selection
AT91C_SSC_CKG_NONE EQU (0x0:SHL:6) ;- (SSC) Receive/Transmit Clock Gating: None, continuous clock
AT91C_SSC_CKG_LOW EQU (0x1:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF Low
AT91C_SSC_CKG_HIGH EQU (0x2:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF High
AT91C_SSC_START EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection
AT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
AT91C_SSC_START_TX EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start
AT91C_SSC_START_LOW_RF EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input
AT91C_SSC_START_HIGH_RF EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input
AT91C_SSC_START_FALL_RF EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input
AT91C_SSC_START_RISE_RF EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input
AT91C_SSC_START_LEVEL_RF EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input
AT91C_SSC_START_EDGE_RF EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input
AT91C_SSC_START_0 EQU (0x8:SHL:8) ;- (SSC) Compare 0
AT91C_SSC_STOP EQU (0x1:SHL:12) ;- (SSC) Receive Stop Selection
AT91C_SSC_STTDLY EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay
AT91C_SSC_PERIOD EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection
;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
AT91C_SSC_DATLEN EQU (0x1F:SHL:0) ;- (SSC) Data Length
AT91C_SSC_LOOP EQU (0x1:SHL:5) ;- (SSC) Loop Mode
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -