📄 at91sam7se512.inc
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;- -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
AT91C_WDTC_WDRSTT EQU (0x1:SHL:0) ;- (WDTC) Watchdog Restart
AT91C_WDTC_KEY EQU (0xFF:SHL:24) ;- (WDTC) Watchdog KEY Password
;- -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
AT91C_WDTC_WDV EQU (0xFFF:SHL:0) ;- (WDTC) Watchdog Timer Restart
AT91C_WDTC_WDFIEN EQU (0x1:SHL:12) ;- (WDTC) Watchdog Fault Interrupt Enable
AT91C_WDTC_WDRSTEN EQU (0x1:SHL:13) ;- (WDTC) Watchdog Reset Enable
AT91C_WDTC_WDRPROC EQU (0x1:SHL:14) ;- (WDTC) Watchdog Timer Restart
AT91C_WDTC_WDDIS EQU (0x1:SHL:15) ;- (WDTC) Watchdog Disable
AT91C_WDTC_WDD EQU (0xFFF:SHL:16) ;- (WDTC) Watchdog Delta Value
AT91C_WDTC_WDDBGHLT EQU (0x1:SHL:28) ;- (WDTC) Watchdog Debug Halt
AT91C_WDTC_WDIDLEHLT EQU (0x1:SHL:29) ;- (WDTC) Watchdog Idle Halt
;- -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
AT91C_WDTC_WDUNF EQU (0x1:SHL:0) ;- (WDTC) Watchdog Underflow
AT91C_WDTC_WDERR EQU (0x1:SHL:1) ;- (WDTC) Watchdog Error
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_VREG
VREG_MR # 4 ;- Voltage Regulator Mode Register
;- -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
AT91C_VREG_PSTDBY EQU (0x1:SHL:0) ;- (VREG) Voltage Regulator Power Standby Mode
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Memory Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_MC
MC_RCR # 4 ;- MC Remap Control Register
MC_ASR # 4 ;- MC Abort Status Register
MC_AASR # 4 ;- MC Abort Address Status Register
# 4 ;- Reserved
MC_PUIA # 64 ;- MC Protection Unit Area
MC_PUP # 4 ;- MC Protection Unit Peripherals
MC_PUER # 4 ;- MC Protection Unit Enable Register
# 8 ;- Reserved
MC0_FMR # 4 ;- MC Flash Mode Register
MC0_FCR # 4 ;- MC Flash Command Register
MC0_FSR # 4 ;- MC Flash Status Register
MC0_VR # 4 ;- MC Flash Version Register
MC1_FMR # 4 ;- MC Flash Mode Register
MC1_FCR # 4 ;- MC Flash Command Register
MC1_FSR # 4 ;- MC Flash Status Register
MC1_VR # 4 ;- MC Flash Version Register
;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
AT91C_MC_RCB EQU (0x1:SHL:0) ;- (MC) Remap Command Bit
;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
AT91C_MC_UNDADD EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status
AT91C_MC_MISADD EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status
AT91C_MC_MPU EQU (0x1:SHL:2) ;- (MC) Memory protection Unit Abort Status
AT91C_MC_ABTSZ EQU (0x3:SHL:8) ;- (MC) Abort Size Status
AT91C_MC_ABTSZ_BYTE EQU (0x0:SHL:8) ;- (MC) Byte
AT91C_MC_ABTSZ_HWORD EQU (0x1:SHL:8) ;- (MC) Half-word
AT91C_MC_ABTSZ_WORD EQU (0x2:SHL:8) ;- (MC) Word
AT91C_MC_ABTTYP EQU (0x3:SHL:10) ;- (MC) Abort Type Status
AT91C_MC_ABTTYP_DATAR EQU (0x0:SHL:10) ;- (MC) Data Read
AT91C_MC_ABTTYP_DATAW EQU (0x1:SHL:10) ;- (MC) Data Write
AT91C_MC_ABTTYP_FETCH EQU (0x2:SHL:10) ;- (MC) Code Fetch
AT91C_MC_MST0 EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source
AT91C_MC_MST1 EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source
AT91C_MC_SVMST0 EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source
AT91C_MC_SVMST1 EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source
;- -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
AT91C_MC_PROT EQU (0x3:SHL:0) ;- (MC) Protection
AT91C_MC_PROT_PNAUNA EQU (0x0) ;- (MC) Privilege: No Access, User: No Access
AT91C_MC_PROT_PRWUNA EQU (0x1) ;- (MC) Privilege: Read/Write, User: No Access
AT91C_MC_PROT_PRWURO EQU (0x2) ;- (MC) Privilege: Read/Write, User: Read Only
AT91C_MC_PROT_PRWURW EQU (0x3) ;- (MC) Privilege: Read/Write, User: Read/Write
AT91C_MC_SIZE EQU (0xF:SHL:4) ;- (MC) Internal Area Size
AT91C_MC_SIZE_1KB EQU (0x0:SHL:4) ;- (MC) Area size 1KByte
AT91C_MC_SIZE_2KB EQU (0x1:SHL:4) ;- (MC) Area size 2KByte
AT91C_MC_SIZE_4KB EQU (0x2:SHL:4) ;- (MC) Area size 4KByte
AT91C_MC_SIZE_8KB EQU (0x3:SHL:4) ;- (MC) Area size 8KByte
AT91C_MC_SIZE_16KB EQU (0x4:SHL:4) ;- (MC) Area size 16KByte
AT91C_MC_SIZE_32KB EQU (0x5:SHL:4) ;- (MC) Area size 32KByte
AT91C_MC_SIZE_64KB EQU (0x6:SHL:4) ;- (MC) Area size 64KByte
AT91C_MC_SIZE_128KB EQU (0x7:SHL:4) ;- (MC) Area size 128KByte
AT91C_MC_SIZE_256KB EQU (0x8:SHL:4) ;- (MC) Area size 256KByte
AT91C_MC_SIZE_512KB EQU (0x9:SHL:4) ;- (MC) Area size 512KByte
AT91C_MC_SIZE_1MB EQU (0xA:SHL:4) ;- (MC) Area size 1MByte
AT91C_MC_SIZE_2MB EQU (0xB:SHL:4) ;- (MC) Area size 2MByte
AT91C_MC_SIZE_4MB EQU (0xC:SHL:4) ;- (MC) Area size 4MByte
AT91C_MC_SIZE_8MB EQU (0xD:SHL:4) ;- (MC) Area size 8MByte
AT91C_MC_SIZE_16MB EQU (0xE:SHL:4) ;- (MC) Area size 16MByte
AT91C_MC_SIZE_64MB EQU (0xF:SHL:4) ;- (MC) Area size 64MByte
AT91C_MC_BA EQU (0x3FFFF:SHL:10) ;- (MC) Internal Area Base Address
;- -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
;- -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
AT91C_MC_PUEB EQU (0x1:SHL:0) ;- (MC) Protection Unit enable Bit
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_EFC
EFC_FMR # 4 ;- MC Flash Mode Register
EFC_FCR # 4 ;- MC Flash Command Register
EFC_FSR # 4 ;- MC Flash Status Register
EFC_VR # 4 ;- MC Flash Version Register
;- -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register --------
AT91C_MC_FRDY EQU (0x1:SHL:0) ;- (EFC) Flash Ready
AT91C_MC_LOCKE EQU (0x1:SHL:2) ;- (EFC) Lock Error
AT91C_MC_PROGE EQU (0x1:SHL:3) ;- (EFC) Programming Error
AT91C_MC_NEBP EQU (0x1:SHL:7) ;- (EFC) No Erase Before Programming
AT91C_MC_FWS EQU (0x3:SHL:8) ;- (EFC) Flash Wait State
AT91C_MC_FWS_0FWS EQU (0x0:SHL:8) ;- (EFC) 1 cycle for Read, 2 for Write operations
AT91C_MC_FWS_1FWS EQU (0x1:SHL:8) ;- (EFC) 2 cycles for Read, 3 for Write operations
AT91C_MC_FWS_2FWS EQU (0x2:SHL:8) ;- (EFC) 3 cycles for Read, 4 for Write operations
AT91C_MC_FWS_3FWS EQU (0x3:SHL:8) ;- (EFC) 4 cycles for Read, 4 for Write operations
AT91C_MC_FMCN EQU (0xFF:SHL:16) ;- (EFC) Flash Microsecond Cycle Number
;- -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register --------
AT91C_MC_FCMD EQU (0xF:SHL:0) ;- (EFC) Flash Command
AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (EFC) Starts the programming of th epage specified by PAGEN.
AT91C_MC_FCMD_LOCK EQU (0x2) ;- (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (EFC) The lock sequence automatically happens after the programming sequence is completed.
AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (EFC) Set General Purpose NVM bits.
AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (EFC) Clear General Purpose NVM bits.
AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (EFC) Set Security Bit.
AT91C_MC_PAGEN EQU (0x3FF:SHL:8) ;- (EFC) Page Number
AT91C_MC_KEY EQU (0xFF:SHL:24) ;- (EFC) Writing Protect Key
;- -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register --------
AT91C_MC_SECURITY EQU (0x1:SHL:4) ;- (EFC) Security Bit Status
AT91C_MC_GPNVM0 EQU (0x1:SHL:8) ;- (EFC) Sector 0 Lock Status
AT91C_MC_GPNVM1 EQU (0x1:SHL:9) ;- (EFC) Sector 1 Lock Status
AT91C_MC_GPNVM2 EQU (0x1:SHL:10) ;- (EFC) Sector 2 Lock Status
AT91C_MC_GPNVM3 EQU (0x1:SHL:11) ;- (EFC) Sector 3 Lock Status
AT91C_MC_GPNVM4 EQU (0x1:SHL:12) ;- (EFC) Sector 4 Lock Status
AT91C_MC_GPNVM5 EQU (0x1:SHL:13) ;- (EFC) Sector 5 Lock Status
AT91C_MC_GPNVM6 EQU (0x1:SHL:14) ;- (EFC) Sector 6 Lock Status
AT91C_MC_GPNVM7 EQU (0x1:SHL:15) ;- (EFC) Sector 7 Lock Status
AT91C_MC_LOCKS0 EQU (0x1:SHL:16) ;- (EFC) Sector 0 Lock Status
AT91C_MC_LOCKS1 EQU (0x1:SHL:17) ;- (EFC) Sector 1 Lock Status
AT91C_MC_LOCKS2 EQU (0x1:SHL:18) ;- (EFC) Sector 2 Lock Status
AT91C_MC_LOCKS3 EQU (0x1:SHL:19) ;- (EFC) Sector 3 Lock Status
AT91C_MC_LOCKS4 EQU (0x1:SHL:20) ;- (EFC) Sector 4 Lock Status
AT91C_MC_LOCKS5 EQU (0x1:SHL:21) ;- (EFC) Sector 5 Lock Status
AT91C_MC_LOCKS6 EQU (0x1:SHL:22) ;- (EFC) Sector 6 Lock Status
AT91C_MC_LOCKS7 EQU (0x1:SHL:23) ;- (EFC) Sector 7 Lock Status
AT91C_MC_LOCKS8 EQU (0x1:SHL:24) ;- (EFC) Sector 8 Lock Status
AT91C_MC_LOCKS9 EQU (0x1:SHL:25) ;- (EFC) Sector 9 Lock Status
AT91C_MC_LOCKS10 EQU (0x1:SHL:26) ;- (EFC) Sector 10 Lock Status
AT91C_MC_LOCKS11 EQU (0x1:SHL:27) ;- (EFC) Sector 11 Lock Status
AT91C_MC_LOCKS12 EQU (0x1:SHL:28) ;- (EFC) Sector 12 Lock Status
AT91C_MC_LOCKS13 EQU (0x1:SHL:29) ;- (EFC) Sector 13 Lock Status
AT91C_MC_LOCKS14 EQU (0x1:SHL:30) ;- (EFC) Sector 14 Lock Status
AT91C_MC_LOCKS15 EQU (0x1:SHL:31) ;- (EFC) Sector 15 Lock Status
;- -------- EFC_VR : (EFC Offset: 0xc) EFC version register --------
AT91C_EFC_VERSION EQU (0xFFF:SHL:0) ;- (EFC) EFC version number
AT91C_EFC_MFN EQU (0x7:SHL:16) ;- (EFC) EFC MFN
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Serial Parallel Interface
;- *****************************************************************************
^ 0 ;- AT91S_SPI
SPI_CR # 4 ;- Control Register
SPI_MR # 4 ;- Mode Register
SPI_RDR # 4 ;- Receive Data Register
SPI_TDR # 4 ;- Transmit Data Register
SPI_SR # 4 ;- Status Register
SPI_IER # 4 ;- Interrupt Enable Register
SPI_IDR # 4 ;- Interrupt Disable Register
SPI_IMR # 4 ;- Interrupt Mask Register
# 16 ;- Reserved
SPI_CSR # 16 ;- Chip Select Register
# 192 ;- Reserved
SPI_RPR # 4 ;- Receive Pointer Register
SPI_RCR # 4 ;- Receive Counter Register
SPI_TPR # 4 ;- Transmit Pointer Register
SPI_TCR # 4 ;- Transmit Counter Register
SPI_RNPR # 4 ;- Receive Next Pointer Register
SPI_RNCR # 4 ;- Receive Next Counter Register
SPI_TNPR # 4 ;- Transmit Next Pointer Register
SPI_TNCR # 4 ;- Transmit Next Counter Register
SPI_PTCR # 4 ;- PDC Transfer Control Register
SPI_PTSR # 4 ;- PDC Transfer Status Register
;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
AT91C_SPI_SPIEN EQU (0x1:SHL:0) ;- (SPI) SPI Enable
AT91C_SPI_SPIDIS EQU (0x1:SHL:1) ;- (SPI) SPI Disable
AT91C_SPI_SWRST EQU (0x1:SHL:7) ;- (SPI) SPI Software reset
AT91C_SPI_LASTXFER EQU (0x1:SHL:24) ;- (SPI) SPI Last Transfer
;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
AT91C_SPI_MSTR EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode
AT91C_SPI_PS EQU (0x1:SHL:1) ;- (SPI) Peripheral Select
AT91C_SPI_PS_FIXED EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select
AT91C_SPI_PS_VARIABLE EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select
AT91C_SPI_PCSDEC EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode
AT91C_SPI_FDIV EQU (0x1:SHL:3) ;- (SPI) Clock Selection
AT91C_SPI_MODFDIS EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection
AT91C_SPI_LLB EQU (0x1:SHL:7) ;- (SPI) Clock Selection
AT91C_SPI_PCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select
AT91C_SPI_DLYBCS EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects
;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
AT91C_SPI_RD EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data
AT91C_SPI_RPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
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