4.5

针对德州仪器DM270开发板的bootloader,其实现了内核的下载以及文件系统的下载

setup:     file format elf32-littlearm

Disassembly of section .text:

00000004 <_start>:
   4:	e3a000d3 	mov	r0, #211	; 0xd3
   8:	e129f000 	msr	CPSR_all, r0
   c:	eb000001 	bl	18 <hw_ini>
  10:	e3a0d902 	mov	sp, #32768	; 0x8000

00000014 <forever>:
  14:	eafffffe 	b	14 <forever>

00000018 <hw_ini>:
  18:	e1a0900e 	mov	r9, lr
  1c:	eb000064 	bl	1b4 <clock_ini>
  20:	e3a01cff 	mov	r1, #65280	; 0xff00

00000024 <wloop>:
  24:	e2511001 	subs	r1, r1, #1	; 0x1
  28:	1afffffd 	bne	24 <wloop>
  2c:	eb000003 	bl	40 <memcntl_ini>
  30:	eb000078 	bl	218 <sdram_ini>
  34:	eb0000c6 	bl	354 <dsp_ini>

00000038 <done_hwinit>:
  38:	e1a0e009 	mov	lr, r9
  3c:	e1a0f00e 	mov	pc, lr

00000040 <memcntl_ini>:
  40:	e59f00d4 	ldr	r0, [pc, #d4]	; 11c <EXBC_CS1CTRL1A>
  44:	e59f1120 	ldr	r1, [pc, #120]	; 16c <EXBC_CS1CTRL1A_DATA>
  48:	e1c010b0 	strh	r1, [r0]
  4c:	e59f00cc 	ldr	r0, [pc, #cc]	; 120 <EXBC_CS1CTRL1B>
  50:	e59f1118 	ldr	r1, [pc, #118]	; 170 <EXBC_CS1CTRL1B_DATA>
  54:	e1c010b0 	strh	r1, [r0]
  58:	e59f00c4 	ldr	r0, [pc, #c4]	; 124 <EXBC_CS1CTRL2>
  5c:	e59f1110 	ldr	r1, [pc, #110]	; 174 <EXBC_CS1CTRL2_DATA>
  60:	e1c010b0 	strh	r1, [r0]
  64:	e59f00bc 	ldr	r0, [pc, #bc]	; 128 <EXBC_CS2CTRL1>
  68:	e59f1108 	ldr	r1, [pc, #108]	; 178 <EXBC_CS2CTRL1_DATA>
  6c:	e1c010b0 	strh	r1, [r0]
  70:	e59f00b8 	ldr	r0, [pc, #b8]	; 130 <EXBC_CS3CTRL1>
  74:	e59f1100 	ldr	r1, [pc, #100]	; 17c <EXBC_CS3CTRL1_DATA>
  78:	e1c010b0 	strh	r1, [r0]
  7c:	e59f00a8 	ldr	r0, [pc, #a8]	; 12c <EXBC_CS2CTRL2>
  80:	e59f10f8 	ldr	r1, [pc, #f8]	; 180 <EXBC_CS2CTRL2_DATA>
  84:	e1c010b0 	strh	r1, [r0]
  88:	e59f00a4 	ldr	r0, [pc, #a4]	; 134 <EXBC_CS3CTRL2>
  8c:	e59f10f0 	ldr	r1, [pc, #f0]	; 184 <EXBC_CS3CTRL2_DATA>
  90:	e1c010b0 	strh	r1, [r0]
  94:	e59f009c 	ldr	r0, [pc, #9c]	; 138 <EXBC_CS4CTRL1>
  98:	e59f10e8 	ldr	r1, [pc, #e8]	; 188 <EXBC_CS4CTRL1_DATA>
  9c:	e1c010b0 	strh	r1, [r0]
  a0:	e59f0094 	ldr	r0, [pc, #94]	; 13c <EXBC_CS4CTRL2>
  a4:	e59f10e0 	ldr	r1, [pc, #e0]	; 18c <EXBC_CS4CTRL2_DATA>
  a8:	e1c010b0 	strh	r1, [r0]
  ac:	e59f008c 	ldr	r0, [pc, #8c]	; 140 <EXBC_BUSCTRL>
  b0:	e59f10d8 	ldr	r1, [pc, #d8]	; 190 <EXBC_BUSCTRL_DATA>
  b4:	e1c010b0 	strh	r1, [r0]
  b8:	e59f0084 	ldr	r0, [pc, #84]	; 144 <EXBC_BUSRLS>
  bc:	e59f10d0 	ldr	r1, [pc, #d0]	; 194 <EXBC_BUSRLS_DATA>
  c0:	e1c010b0 	strh	r1, [r0]
  c4:	e59f0084 	ldr	r0, [pc, #84]	; 150 <EXBC_DPSTR0>
  c8:	e59f10c8 	ldr	r1, [pc, #c8]	; 198 <EXBC_DPSTR0_DATA>
  cc:	e1c010b0 	strh	r1, [r0]
  d0:	e59f007c 	ldr	r0, [pc, #7c]	; 154 <EXBC_DPSTR1>
  d4:	e59f10c0 	ldr	r1, [pc, #c0]	; 19c <EXBC_DPSTR1_DATA>
  d8:	e1c010b0 	strh	r1, [r0]
  dc:	e59f0074 	ldr	r0, [pc, #74]	; 158 <EXBC_DPSTR2>
  e0:	e59f10b8 	ldr	r1, [pc, #b8]	; 1a0 <EXBC_DPSTR2_DATA>
  e4:	e1c010b0 	strh	r1, [r0]
  e8:	e59f006c 	ldr	r0, [pc, #6c]	; 15c <EXBC_DPSTR3>
  ec:	e59f10b0 	ldr	r1, [pc, #b0]	; 1a4 <EXBC_DPSTR3_DATA>
  f0:	e1c010b0 	strh	r1, [r0]
  f4:	e59f0064 	ldr	r0, [pc, #64]	; 160 <EXBC_DPSTR4>
  f8:	e59f10a8 	ldr	r1, [pc, #a8]	; 1a8 <EXBC_DPSTR4_DATA>
  fc:	e1c010b0 	strh	r1, [r0]
 100:	e59f005c 	ldr	r0, [pc, #5c]	; 164 <EXBC_DPSTR5>
 104:	e59f10a0 	ldr	r1, [pc, #a0]	; 1ac <EXBC_DPSTR5_DATA>
 108:	e1c010b0 	strh	r1, [r0]
 10c:	e59f0054 	ldr	r0, [pc, #54]	; 168 <EXBC_TEST>
 110:	e59f1098 	ldr	r1, [pc, #98]	; 1b0 <EXBC_TEST_DATA>
 114:	e1c010b0 	strh	r1, [r0]
 118:	e1a0f00e 	mov	pc, lr

0000011c <EXBC_CS1CTRL1A>:
 11c:	00030a04 	andeq	r0, r3, r4, lsl #20

00000120 <EXBC_CS1CTRL1B>:
 120:	00030a06 	andeq	r0, r3, r6, lsl #20

00000124 <EXBC_CS1CTRL2>:
 124:	00030a08 	andeq	r0, r3, r8, lsl #20

00000128 <EXBC_CS2CTRL1>:
 128:	00030a0a 	andeq	r0, r3, r10, lsl #20

0000012c <EXBC_CS2CTRL2>:
 12c:	00030a0c 	andeq	r0, r3, r12, lsl #20

00000130 <EXBC_CS3CTRL1>:
 130:	00030a0e 	andeq	r0, r3, lr, lsl #20

00000134 <EXBC_CS3CTRL2>:
 134:	00030a10 	andeq	r0, r3, r0, lsl r10

00000138 <EXBC_CS4CTRL1>:
 138:	00030a12 	andeq	r0, r3, r2, lsl r10

0000013c <EXBC_CS4CTRL2>:
 13c:	00030a14 	andeq	r0, r3, r4, lsl r10

00000140 <EXBC_BUSCTRL>:
 140:	00030a16 	andeq	r0, r3, r6, lsl r10

00000144 <EXBC_BUSRLS>:
 144:	00030a18 	andeq	r0, r3, r8, lsl r10

00000148 <EXBC_CFCTRL1>:
 148:	00030a1a 	andeq	r0, r3, r10, lsl r10

0000014c <EXBC_CFCTRL2>:
 14c:	00030a1c 	andeq	r0, r3, r12, lsl r10

00000150 <EXBC_DPSTR0>:
 150:	00030a4a 	andeq	r0, r3, r10, asr #20

00000154 <EXBC_DPSTR1>:
 154:	00030a4c 	andeq	r0, r3, r12, asr #20

00000158 <EXBC_DPSTR2>:
 158:	00030a4e 	andeq	r0, r3, lr, asr #20

0000015c <EXBC_DPSTR3>:
 15c:	00030a50 	andeq	r0, r3, r0, asr r10

00000160 <EXBC_DPSTR4>:
 160:	00030a52 	andeq	r0, r3, r2, asr r10

00000164 <EXBC_DPSTR5>:
 164:	00030a54 	andeq	r0, r3, r4, asr r10

00000168 <EXBC_TEST>:
 168:	00030a56 	andeq	r0, r3, r6, asr r10

0000016c <EXBC_CS1CTRL1A_DATA>:
 16c:	00001415 	andeq	r1, r0, r5, lsl r4

00000170 <EXBC_CS1CTRL1B_DATA>:
 170:	00001109 	andeq	r1, r0, r9, lsl #2

00000174 <EXBC_CS1CTRL2_DATA>:
 174:	00001220 	andeq	r1, r0, r0, lsr #4

00000178 <EXBC_CS2CTRL1_DATA>:
 178:	00003207 	andeq	r3, r0, r7, lsl #4

0000017c <EXBC_CS3CTRL1_DATA>:
 17c:	0000889a 	muleq	r0, r10, r8

00000180 <EXBC_CS2CTRL2_DATA>:
 180:	00001129 	andeq	r1, r0, r9, lsr #2

00000184 <EXBC_CS3CTRL2_DATA>:
 184:	00005110 	andeq	r5, r0, r0, lsl r1

00000188 <EXBC_CS4CTRL1_DATA>:
 188:	0000aaef 	andeq	r10, r0, pc, ror #21

0000018c <EXBC_CS4CTRL2_DATA>:
 18c:	00006350 	andeq	r6, r0, r0, asr r3

00000190 <EXBC_BUSCTRL_DATA>:
 190:	00000000 	andeq	r0, r0, r0

00000194 <EXBC_BUSRLS_DATA>:
 194:	00000000 	andeq	r0, r0, r0

00000198 <EXBC_DPSTR0_DATA>:
 198:	00000009 	andeq	r0, r0, r9

0000019c <EXBC_DPSTR1_DATA>:
 19c:	00000049 	andeq	r0, r0, r9, asr #32

000001a0 <EXBC_DPSTR2_DATA>:
 1a0:	00000050 	andeq	r0, r0, r0, asr r0

000001a4 <EXBC_DPSTR3_DATA>:
 1a4:	00000051 	andeq	r0, r0, r1, asr r0

000001a8 <EXBC_DPSTR4_DATA>:
 1a8:	00000069 	andeq	r0, r0, r9, rrx

000001ac <EXBC_DPSTR5_DATA>:
 1ac:	00000081 	andeq	r0, r0, r1, lsl #1

000001b0 <EXBC_TEST_DATA>:
 1b0:	00000000 	andeq	r0, r0, r0

000001b4 <clock_ini>:
 1b4:	e59f0104 	ldr	r0, [pc, #104]	; 2c0 <CLKC_PLLA>
 1b8:	e59f1124 	ldr	r1, [pc, #124]	; 2e4 <PLLAOUT_DATA>
 1bc:	e1c010b0 	strh	r1, [r0]
 1c0:	e59f00fc 	ldr	r0, [pc, #fc]	; 2c4 <CLKC_PLLB>
 1c4:	e59f111c 	ldr	r1, [pc, #11c]	; 2e8 <PLLBOUT_DATA>
 1c8:	e1c010b0 	strh	r1, [r0]
 1cc:	e59f00f4 	ldr	r0, [pc, #f4]	; 2c8 <CLKC_CLKC>
 1d0:	e59f1108 	ldr	r1, [pc, #108]	; 2e0 <CLOCKC_DATA>
 1d4:	e1c010b0 	strh	r1, [r0]
 1d8:	e59f00f0 	ldr	r0, [pc, #f0]	; 2d0 <CLKC_DIV>
 1dc:	e59f110c 	ldr	r1, [pc, #10c]	; 2f0 <DIV_DATA>
 1e0:	e1c010b0 	strh	r1, [r0]
 1e4:	e59f00e0 	ldr	r0, [pc, #e0]	; 2cc <CLKC_SEL>
 1e8:	e59f10fc 	ldr	r1, [pc, #fc]	; 2ec <SEL_DATA>
 1ec:	e1c010b0 	strh	r1, [r0]
 1f0:	e59f00dc 	ldr	r0, [pc, #dc]	; 2d4 <CLOCKC_MOD1>
 1f4:	e59f10f8 	ldr	r1, [pc, #f8]	; 2f4 <MOD1_DATA>
 1f8:	e1c010b0 	strh	r1, [r0]
 1fc:	e59f00d4 	ldr	r0, [pc, #d4]	; 2d8 <CLOCKC_MOD2>
 200:	e59f10f0 	ldr	r1, [pc, #f0]	; 2f8 <MOD2_DATA>
 204:	e1c010b0 	strh	r1, [r0]
 208:	e59f00cc 	ldr	r0, [pc, #cc]	; 2dc <CLOCKC_MOD3>
 20c:	e59f10e8 	ldr	r1, [pc, #e8]	; 2fc <MOD3_DATA>
 210:	e1c010b0 	strh	r1, [r0]
 214:	e1a0f00e 	mov	pc, lr

00000218 <sdram_ini>:
 218:	e59f00e0 	ldr	r0, [pc, #e0]	; 300 <SDRAMC_MODE>
 21c:	e59f10e4 	ldr	r1, [pc, #e4]	; 308 <SDMODE_DATA>
 220:	e1c010b0 	strh	r1, [r0]
 224:	e59f00d8 	ldr	r0, [pc, #d8]	; 304 <SDRAMC_REFCTL>
 228:	e59f10dc 	ldr	r1, [pc, #dc]	; 30c <SDREF_DATA>
 22c:	e1c010b0 	strh	r1, [r0]
 230:	e59f00c8 	ldr	r0, [pc, #c8]	; 300 <SDRAMC_MODE>
 234:	e59f10d4 	ldr	r1, [pc, #d4]	; 310 <SDCNT_DATA1>
 238:	e1c010b0 	strh	r1, [r0]
 23c:	e59f10d0 	ldr	r1, [pc, #d0]	; 314 <SDCNT_DATA2>
 240:	e1c010b0 	strh	r1, [r0]
 244:	e1c010b0 	strh	r1, [r0]
 248:	e1c010b0 	strh	r1, [r0]
 24c:	e1c010b0 	strh	r1, [r0]
 250:	e1c010b0 	strh	r1, [r0]
 254:	e1c010b0 	strh	r1, [r0]
 258:	e1c010b0 	strh	r1, [r0]
 25c:	e1c010b0 	strh	r1, [r0]
 260:	e59f10b0 	ldr	r1, [pc, #b0]	; 318 <SDCNT_DATA3>
 264:	e1c010b0 	strh	r1, [r0]
 268:	e59f00ac 	ldr	r0, [pc, #ac]	; 31c <SDRAMC_SDPRTY3>
 26c:	e59f10c4 	ldr	r1, [pc, #c4]	; 338 <SDPTRY3_DATA>
 270:	e1c010b0 	strh	r1, [r0]
 274:	e59f00a4 	ldr	r0, [pc, #a4]	; 320 <SDRAMC_SDPRTY4>
 278:	e59f10bc 	ldr	r1, [pc, #bc]	; 33c <SDPTRY4_DATA>
 27c:	e1c010b0 	strh	r1, [r0]
 280:	e59f009c 	ldr	r0, [pc, #9c]	; 324 <SDRAMC_SDPRTY5>
 284:	e59f10b4 	ldr	r1, [pc, #b4]	; 340 <SDPTRY5_DATA>
 288:	e1c010b0 	strh	r1, [r0]
 28c:	e59f0094 	ldr	r0, [pc, #94]	; 328 <SDRAMC_SDPRTY6>
 290:	e59f10ac 	ldr	r1, [pc, #ac]	; 344 <SDPTRY6_DATA>
 294:	e1c010b0 	strh	r1, [r0]
 298:	e59f008c 	ldr	r0, [pc, #8c]	; 32c <SDRAMC_SDPRTY9>
 29c:	e59f10a4 	ldr	r1, [pc, #a4]	; 348 <SDPTRY9_DATA>
 2a0:	e1c010b0 	strh	r1, [r0]
 2a4:	e59f0084 	ldr	r0, [pc, #84]	; 330 <SDRAMC_SDPRTY10>
 2a8:	e59f109c 	ldr	r1, [pc, #9c]	; 34c <SDPTRY10_DATA>
 2ac:	e1c010b0 	strh	r1, [r0]
 2b0:	e59f007c 	ldr	r0, [pc, #7c]	; 334 <SDRAMC_PRTYON>
 2b4:	e59f1094 	ldr	r1, [pc, #94]	; 350 <PRTYON_DATA>
 2b8:	e1c010b0 	strh	r1, [r0]
 2bc:	e1a0f00e 	mov	pc, lr

000002c0 <CLKC_PLLA>:
 2c0:	00030880 	andeq	r0, r3, r0, lsl #17

000002c4 <CLKC_PLLB>:
 2c4:	00030882 	andeq	r0, r3, r2, lsl #17

000002c8 <CLKC_CLKC>:
 2c8:	00030884 	andeq	r0, r3, r4, lsl #17

000002cc <CLKC_SEL>:
 2cc:	00030886 	andeq	r0, r3, r6, lsl #17

000002d0 <CLKC_DIV>:
 2d0:	00030888 	andeq	r0, r3, r8, lsl #17

000002d4 <CLOCKC_MOD1>:
 2d4:	00030890 	muleq	r3, r0, r8

000002d8 <CLOCKC_MOD2>:
 2d8:	00030892 	muleq	r3, r2, r8

000002dc <CLOCKC_MOD3>:
 2dc:	00030894 	muleq	r3, r4, r8

000002e0 <CLOCKC_DATA>:
 2e0:	00004200 	andeq	r4, r0, r0, lsl #4

000002e4 <PLLAOUT_DATA>:
 2e4:	000080e1 	andeq	r8, r0, r1, ror #1

000002e8 <PLLBOUT_DATA>:
 2e8:	000080c1 	andeq	r8, r0, r1, asr #1

000002ec <SEL_DATA>:
 2ec:	00001011 	andeq	r1, r0, r1, lsl r0

000002f0 <DIV_DATA>:
 2f0:	00000111 	andeq	r0, r0, r1, lsl r1

000002f4 <MOD1_DATA>:
 2f4:	000007ff 	streqsh	r0, [r0], -pc

000002f8 <MOD2_DATA>:
 2f8:	000001ff 	streqsh	r0, [r0], -pc

000002fc <MOD3_DATA>:
 2fc:	00003fff 	streqsh	r3, [r0], -pc

00000300 <SDRAMC_MODE>:
 300:	000309a6 	andeq	r0, r3, r6, lsr #19

00000304 <SDRAMC_REFCTL>:
 304:	000309a8 	andeq	r0, r3, r8, lsr #19

00000308 <SDMODE_DATA>:
 308:	00009f00 	andeq	r9, r0, r0, lsl #30

0000030c <SDREF_DATA>:
 30c:	00000140 	andeq	r0, r0, r0, asr #2

00000310 <SDCNT_DATA1>:
 310:	00009f02 	andeq	r9, r0, r2, lsl #30

00000314 <SDCNT_DATA2>:
 314:	00009f04 	andeq	r9, r0, r4, lsl #30

00000318 <SDCNT_DATA3>:
 318:	00009f01 	andeq	r9, r0, r1, lsl #30

0000031c <SDRAMC_SDPRTY3>:
 31c:	000309ae 	andeq	r0, r3, lr, lsr #19

00000320 <SDRAMC_SDPRTY4>:
 320:	000309b0 	streqh	r0, [r3], -r0

00000324 <SDRAMC_SDPRTY5>:
 324:	000309b2 	streqh	r0, [r3], -r2

00000328 <SDRAMC_SDPRTY6>:
 328:	000309b4 	streqh	r0, [r3], -r4

0000032c <SDRAMC_SDPRTY9>:
 32c:	000309ba 	streqh	r0, [r3], -r10

00000330 <SDRAMC_SDPRTY10>:
 330:	000309bc 	streqh	r0, [r3], -r12

00000334 <SDRAMC_PRTYON>:
 334:	000309be 	streqh	r0, [r3], -lr

00000338 <SDPTRY3_DATA>:
 338:	00000040 	andeq	r0, r0, r0, asr #32

0000033c <SDPTRY4_DATA>:
 33c:	00000020 	andeq	r0, r0, r0, lsr #32

00000340 <SDPTRY5_DATA>:
 340:	00000010 	andeq	r0, r0, r0, lsl r0

00000344 <SDPTRY6_DATA>:
 344:	00000080 	andeq	r0, r0, r0, lsl #1

00000348 <SDPTRY9_DATA>:
 348:	00000001 	andeq	r0, r0, r1

0000034c <SDPTRY10_DATA>:
 34c:	00000002 	andeq	r0, r0, r2

00000350 <PRTYON_DATA>:
 350:	00000001 	andeq	r0, r0, r1

00000354 <dsp_ini>:
 354:	e59f0040 	ldr	r0, [pc, #40]	; 39c <DSP_HPIB_CTL>
 358:	e59f1044 	ldr	r1, [pc, #44]	; 3a4 <DSP_RESET_DATA>
 35c:	e1c010b0 	strh	r1, [r0]
 360:	e1a00000 	nop			(mov r0,r0)
 364:	e1a00000 	nop			(mov r0,r0)
 368:	e1a00000 	nop			(mov r0,r0)
 36c:	e1a00000 	nop			(mov r0,r0)
 370:	e59f0024 	ldr	r0, [pc, #24]	; 39c <DSP_HPIB_CTL>
 374:	e59f102c 	ldr	r1, [pc, #2c]	; 3a8 <DSP_NORMAL_DATA>
 378:	e1c010b0 	strh	r1, [r0]
 37c:	e1a00000 	nop			(mov r0,r0)
 380:	e1a00000 	nop			(mov r0,r0)
 384:	e1a00000 	nop			(mov r0,r0)
 388:	e1a00000 	nop			(mov r0,r0)
 38c:	e59f0008 	ldr	r0, [pc, #8]	; 39c <DSP_HPIB_CTL>
 390:	e59f1014 	ldr	r1, [pc, #14]	; 3ac <DSP_INT0_DATA>
 394:	e1c010b0 	strh	r1, [r0]
 398:	e1a0f00e 	mov	pc, lr

0000039c <DSP_HPIB_CTL>:
 39c:	00030600 	andeq	r0, r3, r0, lsl #12

000003a0 <DSP_HPIB_STAT>:
 3a0:	00030602 	andeq	r0, r3, r2, lsl #12

000003a4 <DSP_RESET_DATA>:
 3a4:	00000689 	andeq	r0, r0, r9, lsl #13

000003a8 <DSP_NORMAL_DATA>:
 3a8:	00000789 	andeq	r0, r0, r9, lsl #15

000003ac <DSP_INT0_DATA>:
 3ac:	00000709 	andeq	r0, r0, r9, lsl #14

000003b0 <L_STACK_MAGIC>:
 3b0:	deadbeef 	cdple	14, 10, cr11, cr13, cr15, {7}

000003b4 <L_STACK_UNTOUCHED_MAGIC>:
 3b4:	feef1ef0 	mcrnv	14, 7, r1, cr15, cr0, {7}
Disassembly of section .data: