📄 hwinit_dm270.s~
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.global sdram_ini .global hw_ini // Save lr so we can returnhw_ini: mov r9, lr // Initialize the board's clocks. bl clock_ini // Pause for SDRAM mov r1, #0xFF00wloop: subs r1, r1, #1 bne wloop //Initialize the network bl lan_ini bl memcntl_ini // Initialize board's SDRAM controller (64MB). bl sdram_ini // Initialize board's HPI memory// bl dsp_ini // A little something for the onboard flash. // bl flashdone_hwinit: mov lr, r9 mov pc, lr// **********************// Macro regw(add,data)// ********************** .macro regw, reg_add, reg_data ldr r0, \reg_add ldr r1, \reg_data strh r1, [r0] .endm// **********************// Macro short_wait()// ********************** .macro short_wait nop nop nop nop .endm // **************************************// Clear out linux command line override.// (see __KernCommandLineOverride of kernel's setup.c) // **************************************//clr_cmdline: // regw CMDLINEOVERRIDE, NULL// mov pc, lr//CMDLINEOVERRIDE: .word 0x00100000//NULL: .word 0x0000 // **************************************// Setup on-board flash.// **************************************//flash: // regw EMIF_CS0CTRL1, CS0CTRL1_DATA// mov pc, lr//EMIF_CS0CTRL1: .word 0x30A00//CS0CTRL1_DATA: .word 0x889A// **************************************// Setup on-board Ethernet.// **************************************lan_ini: // mov r3, lr regw GIO_DIR0, GIO_DIR0_DATA regw GIO_BITSET0, GIO_BITSET0_DATA regw GIO_BITCLR0, GIO_BITCLR0_DATA mov pc, lrGIO_DIR0: .word 0x00030580GIO_INV0: .word 0x00030586GIO_INV1: .word 0x00030588GIO_BITSET0: .word 0x0003058CGIO_BITSET1: .word 0x0003058EGIO_BITCLR0: .word 0x00030592GIO_DIR0_DATA: .word 0x7EDFGIO_BITSET0_DATA: .word 0x0120GIO_BITCLR0_DATA: .word 0x8000// *******************************************************// Memory Controller initialize// *******************************************************memcntl_ini: regw EXBC_CS1CTRL1A, EXBC_CS1CTRL1A_DATA regw EXBC_CS1CTRL1B, EXBC_CS1CTRL1B_DATA regw EXBC_CS1CTRL2, EXBC_CS1CTRL2_DATA regw EXBC_CS2CTRL1, EXBC_CS2CTRL1_DATA regw EXBC_CS3CTRL1, EXBC_CS3CTRL1_DATA regw EXBC_CS2CTRL2, EXBC_CS2CTRL2_DATA regw EXBC_CS3CTRL2, EXBC_CS3CTRL2_DATA regw EXBC_CS4CTRL1, EXBC_CS4CTRL1_DATA regw EXBC_CS4CTRL2, EXBC_CS4CTRL2_DATA regw EXBC_BUSCTRL, EXBC_BUSCTRL_DATA regw EXBC_BUSRLS, EXBC_BUSRLS_DATA regw EXBC_DPSTR0, EXBC_DPSTR0_DATA regw EXBC_DPSTR1, EXBC_DPSTR1_DATA regw EXBC_DPSTR2, EXBC_DPSTR2_DATA regw EXBC_DPSTR3, EXBC_DPSTR3_DATA regw EXBC_DPSTR4, EXBC_DPSTR4_DATA regw EXBC_DPSTR5, EXBC_DPSTR5_DATA //regw EXBC_BUSSTS, EXBC_BUSSTS_DATA regw EXBC_TEST,EXBC_TEST_DATA mov pc, lr/* External Bus *///EXBC_BUSSTS: .word 0x00030a24//EXBC_BUSSTS_DATA: .word 0x000f//EXBC_CS0CTRL1: .word 0x00030a00 //#define EXBC_CS0CTRL2 0x00030a02EXBC_CS1CTRL1A: .word 0x00030a04EXBC_CS1CTRL1B: .word 0x00030a06EXBC_CS1CTRL2: .word 0x00030a08EXBC_CS2CTRL1: .word 0x00030a0aEXBC_CS2CTRL2: .word 0x00030a0cEXBC_CS3CTRL1: .word 0x00030a0eEXBC_CS3CTRL2: .word 0x00030a10EXBC_CS4CTRL1: .word 0x00030a12EXBC_CS4CTRL2: .word 0x00030a14EXBC_BUSCTRL: .word 0x00030a16EXBC_BUSRLS: .word 0x00030a18EXBC_CFCTRL1: .word 0x00030a1aEXBC_CFCTRL2: .word 0x00030a1cEXBC_DPSTR0: .word 0x00030a4aEXBC_DPSTR1: .word 0x00030a4cEXBC_DPSTR2: .word 0x00030a4eEXBC_DPSTR3: .word 0x00030a50EXBC_DPSTR4: .word 0x00030a52EXBC_DPSTR5: .word 0x00030a54EXBC_TEST: .word 0x00030a56EXBC_CS1CTRL1A_DATA: .word 0x1415 /* CE=21w CYC=22w */EXBC_CS1CTRL1B_DATA: .word 0x1109 /* OE=18w WE=10w */EXBC_CS1CTRL2_DATA: .word 0x1220 /* IDLE=1 OE=2 WE=2 CE=0 */EXBC_CS2CTRL1_DATA: .word 0x3207EXBC_CS3CTRL1_DATA: .word 0x889AEXBC_CS2CTRL2_DATA: .word 0x1129EXBC_CS3CTRL2_DATA: .word 0x5110 /* WD=16b IDLE=1 OE=1 CE=0 */EXBC_CS4CTRL1_DATA: .word 0xaaefEXBC_CS4CTRL2_DATA: .word 0x4350EXBC_BUSCTRL_DATA: .word 0x0000 /* Ext wait invalid */EXBC_BUSRLS_DATA: .word 0x0000 /* normal not-open not-open */EXBC_DPSTR0_DATA: .word 0x0009 /* CS0 (FLASH) 10:0000-090:0000 */EXBC_DPSTR1_DATA : .word 0x0029 /* SDRAM 90:0000-290:0000 */EXBC_DPSTR2_DATA: .word 0x0039 /* CS1 (CF) 290:0000-590:0000 */EXBC_DPSTR3_DATA: .word 0x0051 /* CS2 (SM) 510:0000-690:0000 */EXBC_DPSTR4_DATA: .word 0x0053 /* CS3 690:0000-790:0000 */EXBC_DPSTR5_DATA: .word 0x0081 /* CS4 ether 790:0000-810:0000 */EXBC_TEST_DATA : .word 0x0000 /* Normal mode */clock_ini: regw CLKC_PLLA, PLLAOUT_DATA regw CLKC_PLLB, PLLBOUT_DATA regw CLKC_CLKC, CLOCKC_DATA regw CLKC_DIV, DIV_DATA regw CLKC_SEL, SEL_DATA regw CLOCKC_MOD1, MOD1_DATA regw CLOCKC_MOD2, MOD2_DATA regw CLOCKC_MOD3, MOD3_DATA mov pc, lr // *******************************************************// SDRAM initialize (and SDRAM precharge)// // Obviously, there's a lot of redundant work// being done here. Reloading r0 and r1 with values they// already have looks silly. But I don't know if the// precharge of the RAM will work if I hammer it 8// times in a row without the intervening reads. So// I'll keep TI's timing.// *******************************************************sdram_ini: regw SDRAMC_MODE, SDMODE_DATA regw SDRAMC_REFCTL, SDREF_DATA ldr r0, SDRAMC_MODE ldr r1, SDCNT_DATA1 strh r1, [r0] ldr r1, SDCNT_DATA2 // Repeat 8 times strh r1, [r0] strh r1, [r0] strh r1, [r0] strh r1, [r0] strh r1, [r0] strh r1, [r0] strh r1, [r0] strh r1, [r0] ldr r1, SDCNT_DATA3 strh r1, [r0] // This fixes a rev1 SDRAM refresh problem regw SDRAMC_SDPRTY3, SDPTRY3_DATA regw SDRAMC_SDPRTY4, SDPTRY4_DATA regw SDRAMC_SDPRTY5, SDPTRY5_DATA regw SDRAMC_SDPRTY6, SDPTRY6_DATA regw SDRAMC_SDPRTY9, SDPTRY9_DATA regw SDRAMC_SDPRTY10, SDPTRY10_DATA regw SDRAMC_PRTYON, PRTYON_DATA mov pc, lr @ returnCLKC_PLLA : .word 0x30880CLKC_PLLB : .word 0x30882CLKC_CLKC : .word 0x30884CLKC_SEL : .word 0x30886CLKC_DIV : .word 0x30888CLOCKC_MOD1: .word 0x30890CLOCKC_MOD2: .word 0x30892CLOCKC_MOD3: .word 0x30894CLOCKC_DATA: .word 0x4200PLLAOUT_DATA: .word 0x80E1 PLLBOUT_DATA: .word 0x80C1 //ARM Clock used PLLB; DSP Clock used PLLB; SDRAM Clock used PLLASEL_DATA : .word 0x1011 DIV_DATA : .word 0x0111 MOD1_DATA: .word 0x07FFMOD2_DATA: .word 0x01FFMOD3_DATA: .word 0x3FFFSDRAMC_MODE: .word 0x309A6SDRAMC_REFCTL: .word 0x309A8//set CASL 3 cycles 9F->D3SDMODE_DATA: .word 0xD300//SDREF_DATA: .word 0x0140SDREF_DATA: .word 0x1140SDCNT_DATA1: .word 0xD302SDCNT_DATA2: .word 0xD304SDCNT_DATA3: .word 0xD301SDRAMC_SDPRTY3: .long 0x309AESDRAMC_SDPRTY4: .long 0x309B0SDRAMC_SDPRTY5: .long 0x309B2SDRAMC_SDPRTY6: .long 0x309B4SDRAMC_SDPRTY9: .long 0x309BA // DSP CPUSDRAMC_SDPRTY10: .long 0x309BC // SDRAM RefreshSDRAMC_PRTYON: .long 0x309BESDPTRY3_DATA: .word 0x0040SDPTRY4_DATA: .word 0x0020SDPTRY5_DATA: .word 0x0010SDPTRY6_DATA: .word 0x0080SDPTRY9_DATA: .word 0x0001SDPTRY10_DATA: .word 0x0002PRTYON_DATA: .word 0x0001// *******************************************************// DSP (HPI memory) initialize// *******************************************************dsp_ini: regw DSP_HPIB_CTL, DSP_RESET_DATA /* DSP Reset */ short_wait regw DSP_HPIB_CTL, DSP_NORMAL_DATA /* DSP Normal */ short_wait regw DSP_HPIB_CTL, DSP_INT0_DATA /* INT0 establish */ mov pc, lrDSP_HPIB_CTL: .word 0x00030600 /* HPIB Control Register */DSP_HPIB_STAT: .word 0x00030602 /* HPIB Status Register */DSP_RESET_DATA: .word 0x0689DSP_NORMAL_DATA: .word 0x0789DSP_INT0_DATA: .word 0x0709// **********************************************************// Note: These values should stay in sync with linux/kernel.h// **********************************************************L_STACK_MAGIC: .long 0xdeadbeefL_STACK_UNTOUCHED_MAGIC: .long 0xfeef1ef0⌨️ 快捷键说明
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